Fetch Stage - IBM PowerPC 604 User Manual

6.2.1.1.1 Fetch Stage
The fetch stage primarily is responsible for fetching instructions from the instruction cache
and detennining the address of the next instruction to be fetched. Instructions fetched from
the cache are latched into an instruction buff er for subsequent consideration by the decode
stage. The instruction fetching logic is shown in Figure 6-5.
BTAC
Decode Buffer
Decode Prediction
Dispatch Buffer
Dispatch Prediction
Pending Branch Queue { Target 1
Seq
1
(BPU Reservation
i------------1
Station) Target
o
Seq O
Finished Branch { Target O Target 1
Queue
....__....,....-~...._-"T"'""_~
Exceptions
MUX
PC
F
A
R To Cache
Execute Stage Correction
--+---
Number Completed
Complete Stage Correction
Figure 6-5. Instruction Fetch Address Generation
6·8
PowerPC 604 RISC Microproceesor User's Manual