Memory Management Units (Mmus); Cache Implementation - IBM PowerPC 604 User Manual

for the same physical address, in which case, the load operation is delayed until the store
has been written back to the cache, ensuring that the load operation retrieves the correct
data.
The LSU does not allow the following operations to be speculatively performed on
unresolved branches:
• Store operations
• Loading of noncacheable data or cache miss operations
• Loading from direct-store segments
1.2.3 Memory Management Units (MMUs)
The primary functions of the MMUs are to translate logical (effective) addresses to
physical addresses for memory accesses, 1/0 accesses (most 1/0 accesses are assumed to
be memory-mapped), and direct-store accesses, and to provide access protection on blocks
and pages of memory.
The Power PC MMUs and exception model support demand-paged virtual memory. Virtual
memory management permits execution of programs larger than the size of physical
memory; demand-paged implies that individual pages are loaded into physical memory
from system memory only when they are first accessed by an executing program.
The hashed page table is a variable-sized data structure that defines the mapping between
virtual page numbers and physical page numbers. The page table size is a power of 2, and
its starting address is a multiple of its size.
Address translations are enabled by setting bits in the MSR-MSR[IR] enables instruction
address translations and MSR[DR] enables data address translations.
The 604 's MMUs support up to 4 Petabytes (252) of virtual memory and 4 Gigabytes (232)
of physical memory. The MMUs support block address translations, direct-store segments,
and page translation of memory segments. Referenced and changed status are maintained
by the processor for each page to assist implementation of a demand-paged virtual memory
system.
Separate but identical translation logic is implemented for data accesses and for instruction
accesses. The 604 implements two 128-entry, two-way set associative translation lookaside
buffers (TLBs), one for instructions and one for data. These TLBs can be accessed
simultaneously.
1.2.4 Cache Implementation
The 604 implements separate 16-Kbyte, four-way set-associative data and instruction
caches (Harvard architecture). The PowerPC architecture defines the unit of coherency as
a cache block, which for the 604 is a 32-byte (eight-word) line.
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