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6-52
Table 6-2. Instruction Execution Timing (COntlnued)
lnetrucllon
Unit
Cycle (cycle)
Serlallzatlon
eubf
SCIU
1
-
eubfc
SCIU
1
-
eubfe
SCIU
1
Execute
subtle
SCIU
1
-
eubfme
SCIU
1
Execute
eubfze
SCIU
·1
Execute
sync
LSU
-
-
tlbl•
LSU
-
Execute
tlbaync
LSU
-
-
tw
SCIU
1
-
twl
SCIU
1
-
xor
SCIU
1
-
xorl
SCIU
1
-
xorl•
SCIU
1
-
1
These Instructions ara
not
pJpeOned.
They
cannol
be
executed untl the pnwlous
lnstrucllon
In
the
FPU completes;
subsequent
FPU Instructions cannot begin
execution until these Instructions complete.
2
The mtepr (XER) Instruction causes lnslrudlons to be flushed when It executes.
PowerPC 604 RISC Microprocesaor Ueer'e Manual
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