Machine Check Exception (Ox00200); System Reset Exception-Register Settings - IBM PowerPC 604 User Manual

4.5.1 System Reset Exception (Ox00100)
The 604 implements the system reset exception as defined in the PowerPC architecture
(OEA). The system reset exception is a nonmaskable, asynchronous exception signaled to
the processor through the assertion of system-defined signals. In the 604, the exception is
signaled by the assertion of either the SRESET or HRESET inputs, described more fully in
Chapter 7, "Signal Descriptions.".
Table 4-6. System Reset Exception-Register Settings
Register Setting Description
SRRO Set to the effective address of the instruction that the processor would have attempted to execute next
if no exception conditions were present.
SRR1 0
Loaded with equivalent bits from the MSR
1-4 Cleared
5-9 Loaded with equivalent
bits
from the MSR
10-15 Cleared
16-31 Loaded with equivalent bits ol the MSR
Note that
if
the processor state is corrupted to the extent that execution camot resume reliably, the
MSR[RQ bit (SRR1 (30)) is deared.
MSR POW 0 BE 0
ILE
-
FE1 0
EE 0 IP
-
PR 0
IA
0
FP 0 DR 0
ME
-
RI 0
FEO 0 LE Set to value of ILE
SE 0
The SRESET input provides a "warm" reset capability. This input is used to avoid causing
the 604 to perform the entire power-on reset sequence, thereby preserving the contents of
the architected registers. This capability is useful when recovering from certain checkstop
or machine check states. When a system reset exception is taken, instruction execution
continues at offset OxOOlOO from the physical base address indicated by MSR[IP].
4.5.2 Machine Check Exception (Ox00200)
The 604 implements the machine check exception as defined in the PowerPC architecture
(OEA). It conditionally initiates a machine check exception after an address or data parity
error occurred on the bus or in a cache, after receiving a qualified transfer error
acknowledge (TEA) indication on the 604 bus, or after the machine check interrupt (MCP)
signal had been asserted. As defined in the OEA, the exception is not taken if the MSR[ME]
is cleared.
Chapter 4. Exceptions
4-13
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