Sequential Consistency; Sequential Consistency Within A Single Processor; Weak Consistency Between Multiple Processors; Memory Coherency Actions On Store Operations - IBM PowerPC 604 User Manual

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Table 3-2. Memory Coherency Actions on Store Operations
Cache State
Bus Operation
snoop Response
Action
I
RWITM
-mmv
Load data, modify ii, mark M
I
RWITM
~
Retry the RWITM
s
Kill
~
Modify cache, mark M
s
Kill
~
Retry the kiD
E
None
Don1care
Modify cache, mark M
M
None
Don1care
Modify cache
3.5 Sequential Consistency
The following sections describe issues related to sequential consistency with respect to
single processor and multiprocessor systems.
3.5.1 Sequential Consistency Within a Single Processor
The PowerPC architecture requires that all memory operations executed by a single
processor be sequentially consistent with respect to that processor. This means that all
memory accesses appear to be executed in the order specified by the program with respect
to exceptions and
data
dependencies. Note that all potential precise exceptions are resolved
before memory accesses that miss in the cache are forwarded onto the memory queue for
arbitration onto
the
bus.
In
addition, although subsequent memory accesses can address the
cache, full coherency checking between
the
cache and the memory queue is provided to
avoid dependency confilcts.
3.5.2 Weak Consistency between Multiple Processors
The PowerPC architecture requires only weak consistency among processors-that is,
memory accesses between processors need not be sequentially consistent
and
memory
accesses among processors can occur in any order. The ability to order memory accesses
weakly provides opportunities for more efficient use of the system bus. Unless a
dependency exists,
the
604 allows read operations to precede store operations.
Note that sttong ordering of memory accesses with respect to
the
bus (and therefore, as
observed by other processors and other bus participants) can be accomplished by following
instructions that access memory with the SYNC instruction.
Chapt• 3. Cache and Bus Interface Unit Operation
3-9

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