IBM PowerPC 604 User Manual page 78

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The MMCRO can
be
written
to
or read only in supervisor mode. The MMCRO includes
controls, such as counter enable control, counter overflow interrupt control, counter event
selection, and counter freeze control.
This register must
be
cleared at power up. Reading this register does not change its
contents. The fields of the register are defined in Table 2-4.
Table 2·4. MMCRO Bit Settings
Bit Name
Description
0 DIS Disable counting unconditionally
0
The values of the PMCn counters can be changed by hardware.
1
The values of the PMCn counters cannot be changed by hardware.
1 DP Disable counting while in supervisor mode
0 The PMCn counters can be changed by hardware.
1 If the processor
is In supervisor mode (MSR(PR] is cleared), the counters
are not changed by hardware.
2
DU Disable counting while In user mode
0 The PMCn counters can be changed by hardware.
1 If the processor is in user mode (MSR[PR] Is set), the PMC counters are
not
changed by hardware.
3
OMS
Disable counting while MSR(PM] is set
0 The PMCn counters can be changed by hardware.
1 If MSR(PM] Is set, the PMCn counters are not changed by hardware.
4 DMR Disable counting while MSR(PM)
Is
zero.
0 The PMCn counters can be changed by hardware.
1 If MSR(PM] is cleared, the PMCn counters are net changed by hardware.
5 ENINT Enable performance monitoring interrupt signaling.
0 Interrupt signaling is disabled.
1 Interrupt signaling is enabled.
This bit Is cleared by hardware when a perlormance monitor Interrupt is signaled.
To reenable these interrupt signals, software must set this bit after servicing the
perlormance monitor interrupt. The IPL ROM code clears this bit before passing
control to the operating system.
6 DISCOUNT Disable counting of PMC1 and PMC2 when a performance monitor interrupt is
signaled (that is, ((PMCnlNTCONTROL = 1)
&
(PMCn(O]
=
1)
&
(ENINT = 1)) or
the occurrence
of
an enabled time base transition with ((INTONBITTRANS =1)
&
(ENINT
=
1)).
0 The signalfing of a performance monitoring interrupt has no effect on the
counting status of PMC1 and PMC2.
1 The signalling of a performance monitoring interrupt prevents the changing
of the PMC1 counter. The PMC2 counter will not change if
PMC2COUNTCTL
=
0.
Because a time base signal could have occurred along with an enabled counter
negative concfltion, software should always reset INTONBITTRANS to zero, if the
value In INTONBITTRANS
was
a one.
7-8
RTCSELECT 64-bit time base, bit selection enable
00
Pick bit 63 to count
01 Pick bit 55 to count
10
Pick bil 51 to count
11
Pick bit 47 to count
2-12
PowerPC 604 RISC Microprocesaor User's Manual