IBM PowerPC 604 User Manual page 60

The PowerPC architecture supports the following types of exceptions:
• Synchronous, precise-These are caused by instructions. All instruction-caused -
exceptions are handled precisely; that is, the machine state at the time the exception
occurs is known and can be completely restored
• Synchronous, imprecise-The PowerPC architecture defines two imprecise
floating-point exception modes, recoverable and nonrecoverable. The 604
implements only the imprecise nonrecoverable mode. The imprecise, recoverable
mode is treated as the precise mode in the 604.
• Asynchronous-The OEA portion of the PowerPC architecture defines two types of
asynchronous exceptions:
- Asynchronous, maskable-The PowerPC architecture defines the external
interrupt and decrementer interrupt, which are rnaskable and asynchronous
exceptions. In the 604, and in many Power PC processors, the hardware interrupt
is generated by the assertion of the Interrupt (INT) signal, which is not defined
by the architecture. In addition, the 604 implements the system management
interrupt, which performs similarly to the external interrupt, and is generated by
the assertion of the System Management Interrupt (SMI) signal, and the
performance monitor interrupt.
When these exceptions occur, their handling is postponed until all instructions,
and any exceptions associated with those instructions, complete execution.
These exceptions are maskable by setting MSR[EE].
- Asynchronous, nonrnaskable-There are two nonrnaskable asynchronous
exceptions that are imprecise: system reset and machine check exceptions. Note
that the OEA portion of the PowerPC architecture, which defines how these.
exceptions work, does not define the causes or the signals used to cause these
exceptions. These exceptions may not be recoverable, or may provide a limited
degree of recoverability for diagnostic purposes.
The PowerPC architecture defines two bits in the machine state register (MSR)-FEO and
FEl-that determine how floating-point exceptions are handled. There are four
combinations of bit settings, of which the 604 implements three. These are as follows:
• Ignore exceptions mode (FEO =FE 1 = 0). In this mode, the instruction dispatch logic
feeds the FPU as fast as possible and the FPU uses an internal pipeline to allow
overlapped execution of instructions. In this mode, floating-point exception
conditions return a predefined value instead of causing an exception.
• Precise interrupt mode (FEO = 1; FEl = x). This mode includes both the precise
mode and imprecise recoverable mode defined in the PowerPC architecture. In this
mode, a floating-point instruction that causes a floating-point exception brings the
machine to a precise state. In doing so, the 604 takes floating-point exceptions as
defined by the PowerPC architecture.
Chapter 1. Overview
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