Mmu Instructions And Register Summary - IBM PowerPC 604 User Manual

-
Table 5-4. Other MMU Exception Conditions for the PowerPC 604 Processor
Condition
Description
Exception
dcbzwithW=1orl=1
dcbz instruction to write-through or Alignment exception (not
cache-inhbited segment or block required by architecture for
this condition)
dcbz when the data cache is The dcbz instruction takes an alignment Alignment exception
locked
exception if the data cache is locked (HIDO
bits 18 and 19) when it is executed.
lwanc or stwcx. with W = 1
Reservation instruction to write-through OSI exception DSISR[S] = 1
segment or block
11Nanc,st1NCX..,echovx,or8C01111X Reservation instruction or external control
OSI exception
instruction to direct-store segment
instruction when SR[l] =1
DSISR[SJ = 1
Floating-point load or store to FP memory access when SR[T] =1 A6gnment exception (not
direct-store segment required by architecture)
Load or store that results in a Direct-store interface protocol signalled with OSI exception
direct-store error
an error condition
DSISR[O) = 1
eclwx or ecowx attempted when
echovx or ecowx attempted with EAR[E] =
o
OSI exception
external control facility disabled DSISR[11] = 1
lmw, stmw, lswl, lswx, stswl, or lmw, stmw, lswl, lswx, stswl, or stswx Alignment exception
stswx instruction atte111>ted in instruction attempted while MSR[LE] = 1
little-endian mode
Operand misalignment Translation enabled and operand is Alignment exception (some
misaligned as descrbed in Chapter 4, of these cases are
"Exceptions." implementation-specific)
5.1.8 MMU Instructions and Register Summary
The MMU instructions and registers provide the operating system with the ability to set up
the block address translation areas and the page tables in memory.
Note that because the implementation of TLBs is optional, the instructions that refer to
these structures are also optional. However, as these structures serve as caches of the page
table, the architecture specifies a software protocol for maintaining coherency between
these caches and the tables in memory whenever changes are made to the tables in memory.
When the tables in memory are changed, the operating system purges these caches of the
corresponding entries, allowing the translation caching mechanism to refetch from the
tables when the corresponding entries are required
Note that the 604 implements all TLB-related instructions except tibia, which is treated as
an illegal instruction.
Because the MMU specification for PowerPC processors is so flexible, it is recommended
that the software that uses these instructions and registers be "encapsulated" into
subroutines to minimize the impact of migrating across the family of implementations.
5-18
PowerPC 604 RISC Microprocessor User's Manual