Additional Programming Tips For The Powerpc 604 Processor - IBM PowerPC 604 User Manual

• The eight-entry CR rename buffer is similar to the GPR rename buffer in that an
instruction that modifies a CR field gets one entry. This includes, for example, all
condition register logical instructions and mtcrf instructions that update only one
CR field. When the CR rename buffer is full, dispatch stalls when the next
instruction to be dispatched needs a CR entry. A rename buffer entry becomes
available one cycle after the result is written to the CR.
• Each execution unit has a two-entry reservation station that holds instructions until
they are ready for execution. Instructions cannot be dispatched if the reservation
station is full.
• No following instruction can dispatch in the same cycle as a branch instruction.
• Since instructions are dispatched in program order, a later instruction cannot be
dispatched until
all
earlier ones have.
• There is an interlock mechanism between CTR and LR. After dispatching a move to
CTR/LR or mtcrf with multiple field update, the dispatch stalls on the first branch,
CR logical, move to
CTR/LR,
or mtcrf that update multiple fields until one cycle
after the dispatched move to CTR/LR or mtcrf instruction executes. Those mtcrf
instructions that update multiple fields are execution-serialized.
• The 604 can handle as many as four branch instructions in the execute and complete
stages. The dispatch stalls on the first instruction after the fourth branch until the first
branch completes. · -
• An
instruction cannot be dispatched until all destination registers for the instruction
have been assigned to a rename register.
• An
instruction may not be dispatched if a serialization mode is in effect for the
instruction.
6.6.2 Additional Programming Tips for the PowerPC 604 Processor
The following guidelines should
be
followed when writing assembly code for the 604.
• Interleave memory instructions with integer and floating-point operations.
The 604 has a dedicated LSU that does not require the use of the integer or ftoating-
point units to process memory operations. As a result, when scheduling code for the
604, interleaving memory operations with integer or floating-point instructions
typically result in better performance.
• Interleave integer operations.
Because the 604 has three IUs, it is also possible to interleave multiple, independent
integer operations. Two of these integer units support simple integer operations,
while the third supports complex integer operations such as bit-field manipulation.
• Avoid using instructions that write to multiple registers.
The 604 's dynamic register renaming permits instructions to execute out of order
with respect
to
their original program sequence, which increases overall throughput.
However, in other PowerPC processors, certain instructions including the load/store
Chapter 6. Instruction Timing 6-43