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Table B-1. lnvalld Forms {Excluding Reserved Flelds) {Continued)
rA:O
rAln
rAorrB
SPRNot
Mnemonic
B~:O
or
rA:O
rA:rT:O
Range
In Range
L:1
Implemented
rA:rD
lswl
x
x
lswx
x
x
cmpl
x
cmp
x
cmpll
x
cmpl
x
mtspr
x
mfspr
x
LFSU
x
lfsux
x
lfdu
x
lfdux
x
sttsu
x
slfsux
x
slfdu
x
stfdux
x
B.2 Invalid Forms with Reserved Fields (Bit 31
Exclusive)
Table B-2 lists the invalid instruction forms of the PowerPC architecture that result from a
nonzero reserved field in the instruction encoding. This table takes into consideration all
reserved fields in an instruction that must
be
zero, excluding only those instructions that
would become invalid if only bit 31 were set. Note that any combination of a one being
detected in the instructions field(s) marked X results in an invalid form.
The tlbsync instruction has the same opcode and format as the sync instruction. Setting
bit 31 in the instruction indicates a tlbsync.
Table B-2. lnvalld Forms with Reserved Flelds {Bit 31 Exclusive)
6
6
6
6
9
9
11
11
14
16
21
Mnemonic
6
to
to
to
to
9
to
to
11
to
to
to
15
to
20
21
to
31
10
15
20
29
10
15
15
20
20
20
25
bclr
x
bclrl
x
B-2
PowarPC 604 RISC Microprocessor User's Manual
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