Bus Interface Overview; Memory Operations; Write-Back Mode - IBM PowerPC 604 User Manual

Requests from a mispredicted branch path are selectively removed from the memory
queues when the misprediction is corrected, eliminating unnecessary memory accesses and
reducing traffic on the system bus. The 604 also implements the cache block touch
instructions
(debt and dcbtst)
which allows the processor to schedule bus activity more
efficiently and increase the likelihood of a cache hit.
The data cache is kept coherent using MESI protocol and maintains a separate port so
snooping does not interfere with other bus traffic. Note that coherency is not maintained in
the instruction cache. Instructions are provided by the PowerPC architecture to ensure
coherency in the instruction cache.
Both caches can be disabled, invalidated, or locked by using bits in the HIDO register. For
more information, see Section 2.1.2.3, "Hardware Implementation-Dependent Register O."
For more information about the 604 cache implementation, see Chapter 3, "Cache and Bus
Interface Unit Operation."
6.3.3 Bus Interface Overview
The bus interface unit (BIU) on the 604 is compatible with that on the PowerPC 601 and
603 processors. The BIU supports both tenured and split-transaction modes and can handle
as many as three outstanding pipelined operations. The BIU can complete one or more
write transactions between the address and data tenures of a read transaction. The BIU
provides critical double word first, so the data in the double word requested by the
instruction fetcher or LSU is presented to the cache before the other data in the cache block.
The critical double word is forwarded to the fetcher or to the LSU without having to wait
for the entire cache block to be updated
For more information about the BIU, see Chapter 3, "Cache and Bus Interface Unit
Operation."
6.3.4 Memory Operations
The 604 provides features that provide flexible and efficient accesses to memory in both
single- and multiple-processor systems.
6.3.4.1 Write-Back Mode
When storing data while in write-back mode, store operations for cacheable data do not
necessarily cause an external bus cycle to update memory. Instead, memory updates only
occur on modified line replacements, cache flushes, or when another processor attempts to
access a specific address for which there is a corresponding modified cache entry. For this
reason, write-back mode may be preferred when external bus bandwidth is a potential
bottleneck-for example, in a multiprocessor environment. Write-back mode is also well
suited for data that is closely coupled to a processor, such as local variables.
Chapter 6. Instruction Timing 6-15