IBM PowerPC 604 User Manual page 438

Referenced
(R)
bit maintenance
recording, 5-12, 5-21, 5-22, 5-30
updates, 5-33
Registers
604-specific registers, 2-3, 2-8, 2-53
hardware implementation registers, 2-8
rename register, 6-32
supervisor-level
BAT registers, 2-6
DABR,2-7
DAR,2-6
DEC,2-7
DSISR,2-7
EAR,2-7
HID0,2-8
IABR,2-8
~CR0,2-8,9-6
MSR,2-5
PIR,2-8
PMCl and PMC2, 2-8
PVR,2-6
SDRl register, 2-6
SIA and SDA, 2-8, 2-15, 9-6
SPRGO-SPRG3, 2-7
SPRs for petfonnance monitor, 9-1
SRROISRRl, 2-7
SRs,2-6
time base (TB),
2-7
user-level
CR,2-4
CIR,2-5
FPRO-FPR31, 2-4
FPSCR,2-4
GPRO-GPR31,
2-4
LR,2-5
time base (TB),
2-5
XER,2-5
Rename buffer, l-10, 6-3
Rename register operation, 6-31
Reservation station, 6-2
Reserved instruction class, 2-23
Reset
=HRES==ET-signal, 7-27, 8-51
reset exception, 4-13
SRESET signal, 7-27, 8-51
di, 4-11
Rotate and
shift
instnJctions, A-20
RSRV signal, 7-28, 8-52
RUN signal, 7-29
s
SC,
4-19
SDRl register, 2-6
Segment registers
Index
INDEX
SR description, 2-6
SR manipulation instructions, 2-55, A-27
Tbit,8-38
Segmented
memory model,
see
Memory management
unit
SHD signal, 7-17
SIA and SDA registers, 2-8, 2-15, 9-1, 9-6
Signals
604 signals, overview, 1-16
AO-A31, 7-7
AEK.
7-16
ABB, 7-5, 8-7
address arbitration, 7-3, 8-7
address transfer, 7-7, 8-12
address transfer attribute, 7-9, 8-13
address transfer start, 7-6
APO-AP3, 7-8
APE,7-9
AR1RY,
7-16, 8-24
BG, 7-4, 8-7
BR, 7-4,8-7
checkstop,
8-51
c:i,
7-14
CKSTPJN, 7-26
CKSTP_OOT,
7-26
CLK_OUT,
7-31
configuration, 7-2
COP/scan
intelface,
7-29
CSEO-CSEl, 7-15, 8-30
data
arbitration, 8-8, 8-20
data
bus arbitration, 7-18
data
transfer, 7-20
data
transfer te1D1ination, 7-22, 8-24
DBB, 7-19, 8-8, 8-22
DBDIS,
7-22
DBG, 7-18, 8-8
DDWO,
7-18, 8-8, 8-23, 8-53
DHO-DH31/DLO-DL31, 7-20
DPO-DP7, 7-21
DPE,7-22
DIITRV,
7-23, 8-24, 8-27
GBL, 7-15
HALTED, 7-29
HRESET, 7-27
INT, 7-25, 8-50
U_INT, 7-28
Meli,
7-25
PLL_CFGO-PLL_CFG3, 7-31
processor configuration, 7-28
reset, 8-51
RSRV, 7-28, 8-52
RUN, 7-29
SHD,
7-17
signal configuration, 1-17
SMI,
4-21, 7-25
lndex-7
11111+