IBM PowerPC 604 User Manual page 345

Figure 8-19 shows data-delay controls in a single-beat write operation. Note that all
bidirectional signals are three-stated between bus tenures. Data transfers are delayed in the
following ways:
• The TA signal is held negated to insert wait states in clocks 3 and 4.
• In clock 6, DBG is held negated, delaying the start of the data tenure.
The last access is not delayed (DRTRY is valid only for read operations).
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Figure 8-19. Single-Beat Writes Showing Data Delay Controls
Chapter
a.
System Interface Operation
8-35