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When an external interrupt exception is taken, instruction execution resumes at off set
Ox00500 from the physical base address indicated by MSR[IP].
4.5.6 Alignment Exception (Ox00600)
The 604 implements
the
alignment exception as defined by the PowerPC architecture
(OEA).
An
alignment exception is initiated when any of the following conditions are met:
• A floating-point load or store, lmw, stmw, lwarx, or stwcx. instruction is not word-
aligned
• If
a floating-point number is not word-aligned. The 604 provides hardware support
for misaligned storage accesses for other memory access instructions.
If
a
misaligned memory access crosses a 4-Kbyte page boundary within a memory
segment, an exception may occur when the boundary is crossed (that is, there is a
protection violation on an attempt
to
access the new page). In these cases, a OSI
exception occurs and the instruction may complete partially.
• Some types of misaligned memory accesses are slower than aligned accesses.
Accesses that cross a word boundary (and double-precision values aligned on a
double-word boundary) are broken into multiple accesses by the LSU. More
dramatically, any noncacheable memory access that crosses a double-word
boundary requires multiple external bus tenures.
• Operations that cross a word boundary (and operations involving double-precision
values aligned on a double-word boundary) require two accesses, which are
translated separately.
If
either translation creates a OSI exception condition, that
exception is signaled.
• If
the T-bit settings are not the same for both portions of a misaligned memory
access, (which is considered to be a programming error), the 604 completes all of
the accesses for the operation, the segment information from the T
=
1 space is
presented on the bus for every access of the operation, and the 604 requires a direct-
store access reply from the device.
If
two translations cross memory locations that
are T
=
0 into T
=
1, a OSI exception is signaled.
• A dcbz instruction references a page that is marked either cache-inhibited or write-
through or has executed when the 604 data cache is locked or disabled Note that this
condition may not cause an alignment exception in other PowerPC processors.
• An
access is not naturally aligned in little-endian mode.
• An
ecowx or eciwx is not word-aligned.
• A lmw, stmw, lswi, lswx, stswi, or stswx instruction is issued in little-endian mode.
4.5. 7 Program Exception (Ox00700)
The 604 implements the program exception as it is defined by the PowerPC architecture
(OBA). A program exception occurs when no higher priority exception exists and one or
more of the exception conditions defined in the OBA occur.
The 604 invokes the system illegal instruction program exception when it detects any
instruction from the illegal instruction class.
Chapter 4. Exceptions
4-17
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