Pmc2 Selectable Events - IBM PowerPC 604 User Manual

9.1.1.1.2 PMC2 Selectable Events
The events counted by PMC2 follow the same groupings explained in the previous section.
The differences between PMCl and PMC2 event selection are as follows:
• Different bits of the MMCRO register are decoded in order to select events.
• PMC2 has fewer events.
Events selectable for counting by
PMC2
are listed. along with their
MMCR0[26-31]
encodings,
are listed in Table 9-3.
Table 9-3. PMC2 Events-MMCRO [26-31) Select Encoding
Encoding Description
000000 Nothing. Register counter holds current value
000001 Processor cycles
00 0010 Numberof instructions completed. Legal values are 000, 001, 010, 011, and 100.
00 0011 RTCSELECT
bit
transition. O
=
47, 1
=
51, 2
=
55, 3
=
63 bits from the time base lower register.
000100 Number of instructions dispatched
00 0101 Number of cycles a load miss takes
00 0110 Data cache misses (data cache line fill)
00 0111 Number of lttb misses
001000
Number of branches completed. Indicates the number ol branch instructions completed every cycle.
00 None
01 Illegal value
10
One
11 Two
001001 Number of reservations successfully obtained
001010 Number of mfspr instructions dispatched (speculative)
00 1011 Number of lcbl instructions. The lcbl instruction may not hit in the cache.
00 1100
Number of pipeline-flushing operations (sc, lsync, mtspr[xer], floating-point operations with divide
by O or invalid operand when the 604 is in precise mode, branch when MSR[BE] is set, lswx with
XER
=
0 and SO set).
001101
Branch unit produced result (branch or CR-logical instruction finished)
00 1110 SCIUO unit produced result (add, subtract, compare, rotate, shift, or logical Instruction)
00 1111 MCIU unit produced result (multiply/divide or SPR instruction)
010000 Number of instructions dispatched to the branc;h unit
01 0001 Number of instructions dispatched to the SCIUO unit
01 0010 Number of loads completed. From Oto 4 instructions per cycle. Indicates the number of load
instructions being completed every cycle. These include all cache operations, tlble, tlbsync, sync,
elelo, and lcbl.
01 0011 Number of instructions dispatched to the MCIU
01 0100 Number of snoop hits occurred
Chapter 9. Performance Monitor
9-5