IBM PowerPC 604 User Manual page 240

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Bus Interface
Load/Store Unit
Line-Fill Buffer
' '
Store Queue
Load Queue
Data Cache
Store Miss
Load Miss
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Queue Queue
Result Buses
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Figure
6-6.
Data caches and Memory Queues
For a load operation, the cache is accessed first by the LSU and data is forwarded to the
execution unit and to the rename buff er if the access hits in the cache. Otherwise, the load
operation is added to the load queue.
Store operations are added to the store queue after they are successfully translated. As each
store operation is completed with respect to the execution unit, it is only marked as
completed in the queue so instruction processing can continue without having to wait for
the actual store operation to take place either in the cache or in system memory. When the
cache is not busy, one completed store can be written to the cache per cycle. In the case of
a cache miss on a store operation, that store inf onnation is placed in the store miss queue
to allow subsequent store operations to continue while the missing cache block is brought
in from system memory. The store queue can hold six instructions.
As each load miss completes, the cache is accessed a second time.
If it misses again, the
instruction is moved to the load miss register while the missing cache block is brought in.
This allows a second load miss to begin without having to wait for the first one to complete.
The load queue can hold as many as four instructions.
6-14 PowerPC 604 RISC Microprocessor Uaer's Manual