Memory Control Instructions-Vea; User-Level Cache Instructions-Vea - IBM PowerPC 604 User Manual

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System designs that use a second-level cache should take special care to recognize the
hardware signaling caused by a SYNC bus operation and perform the appropriate actions
to guarantee that memory references that may be queued internally to the second-level
cache have been performed globally.
In addition to the sync instruction (specified by VISA), the VEA defines the Enforce
In-Order Execution of 1/0 (eieio) and Instruction Synchronize (isync) instructions. The
number of cycles required to complete an eieio instruction depends on system parameters
and on the processor's state when the instruction is issued. As a result, frequent use of this
instruction may degrade performance slightly.
The isync instruction causes the processor to wait for any preceding instructions to
complete, discard all prefetched instructions, and then branch to the next sequential
instruction (which has the effect of clearing the pipeline behind the isync instruction).
2.3.5.3 Memory Control Instructions-VEA
Memory control instructions include the following types:
• Cache management instructions (user-level and supervisor-level)
• Segment register manipulation instructions
• Translation lookaside buff er management instructions
This section describes the user-level cache management instructions defined by the VEA.
See 2.3.6.3, "Memory Control Instructions-OEA," for information about supervisor-level
cache, segment register manipulation, and translation lookaside buffer management
instructions.
2.3.5.3.1 User-Level Cache Instructions-VEA
The instructions summarized in this section provide user-level programs the ability to
manage on-chip caches if they are implemented. See Chapter 3, "Cache and Bus Interface
Unit Operation," for more information about cache topics.
The user-level cache instructions provide software a way to help manage processor caches.
The following sections describe how these operations are treated with respect to the 604's
cache.
As with other memory-related instructions, the effect of the cache management instructions
on memory are weakly-ordered. If the programmer needs to ensure that cache or other
instructions have been performed with respect to all other processors and system
mechanisms, a sync instruction must be placed in the program following those instructions.
Note that this discussion does not apply to direct-store segment accesses because these are
defined to be cache-inhibited and instruction fetch from them is not allowed Cache
operations that access direct-store segment are treated as no-ops. Table 2-38 summarizes
the cache instructions defined by the VEA. Note that these instructions are accessible to
user-level programs.
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