Transfer Acknowledge; Data Retry - IBM PowerPC 604 User Manual

7 .2.8.1 Transfer Acknowledge (TA)-lnput
The ttansfer acknowledge (TA) signal is an input signal (input-only) on the 604. Following
are the state meaning and timing comments for the TA signal.
State Meaning
Asserted- Indicates that a single-beat data ttansfer completed
successfully or that a data beat in a burst ttansfer completed
successfully (unless DRTRY is asserted on the next bus clock cycle).
Note that TA must be asserted for each data beat in a burst
ttansaction. For more information, see Section 8.4.4, "Data Transfer
Termination."
Negated-{During DBB) indicates that, until TA is asserted, the 604
must continue to drive the data for the current write or must wait
to
sample the data for reads.
Timing
Comments
Assertion-When the bus is configured for normal operation, must
not occur earlier than one bus clock cycle before the beginning of the
valid ARTRY window, or when the bus is configured for fast-L2
mode, must not be asserted earlier than the first cycle of a valid
ARTRY window; otherwise, assertion may occur at any time during
the assertion of DBB. The system can withhold assertion of TA
to
indicate that the 604 should
insert
wait states
to
extend the duration
of the data beat.
Negation-Must occur after the bus clock cycle of the
final
(or onl_u
data beat of the ttansfer. For a burst ttansfer, the system can assert TA
for one bus clock cycle and then negate it
to
advance the burst
ttansfer
to
the next beat and
insert
wait states during the next beat.
7 .2.8.2 Data Retry (DRTRY)-lnput
The data retty (DRTRY) signal is input only on the 604. Following are the state meaning
and
timing comments for the DRTRY signal.
State Meaning
Asserted-Indicates that the 604 must invalidate the data from the
previous read operation.
Negated-Indicates that data presented with TA on the previous read
operation is valid. This
is~entia:lly
a late TA
to
allow speculative
forwarding of
data
(with TA) during reads. Note that DRTRY is
ignored for write ttansactions.
Chapter 7. Signal Descriptions
7.23