Selection Of Page Address Translation; Selection Of Direct-Store Interface Address Translation; Mmu Exceptions Summary - IBM PowerPC 604 User Manual

5.1.6.3 Selection of Page Address Translation
If
the T bit in the corresponding segment descriptor is 0, page address translation is
selected The information in the segment descriptor is then used to generate the 52-bit
virtual address. The virtual address is then used to identify the page address translation
information (stored as page table entries (PTEs) in a page table in memory). For increased
performance, the 604 has two on-chip TLBs to store recently-used PTEs on-chip.
If an access hits in the appropriate TLB, the page translation occurs and the physical
address bits are forwarded to the memory subsystem. If the required PTE is not resident,
the MMU requires a search of the page table. In this case, the 604 hardware performs the
page table search operation. If the PTE is successfully found, a new TLB entry is created
and the page translation is once again attempted This time, the TLB is guaranteed to hit.
Once the PTE is located, the access is qualified with the appropriate protection bits. If the
access is a protection violation (not allowed), either an ISi or OSI exception is generated.
If the PTE is not found by the table search operation, a page fault condition exists, and an
ISi or DSI exception occurs so software can handle the page fault.
5.1.6.4 Selection of Direct-Store Interface Address Translation
When the segment descriptor has the T bit set, the access is considered a direct-store
interface access and the direct-store interface protocol of the external interface is used to
perform the access to direct-store space. The selection of address translation type differs for
instruction and data accesses only in that instruction accesses are not allowed from
direct-store segments; attempting
to
fetch an instruction from a direct-store segment causes
an ISi exception. See Section 5.5, "Direct-Store Interface Address Translation," for more
detailed information about the translation of addresses in direct-store space.
5.1.7 MMU Exceptions Summary
In order to complete any memory access, the effective address must be translated to a
physical address. As specified by the architecture, an MMU exception condition occurs if
this translation fails for one of the following reasons:
• There is no valid entry in the page table for the page specified by the effective
address (and segment descriptor) and there is no valid BAT translation.
• An address translation is found but the access is not allowed by the memory
protection mechanism.
The translation exception conditions defined by the OEA for 32-bit implementations cause
either the ISi or the OSI exception to be taken as shown in Table 5-3.
The state saved by the processor for each of these exceptions contains information that
identifies the address of the failing instruction. Refer to Chapter 4, "Exceptions," for a more
detailed description of exception processing.
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PowerPC 604 RISC Microprocessor User's Manual