IBM PowerPC 604 User Manual page 310

Table 7-6. PLL Configuration (Continued)
Bus, CPU and PLL Frequencies
PLL_CFG
CPU/
Bus Bus Bus Bus Bus Bus Bus
SYSCLK
0-4
Ratio
16.&MHz 20MHz 25MHz 33.3MHz 40MHz 50MHz
66.&MHz
1000 3:1
-
-
75 100
- - -
(150) (200)
1100 1.5:1
- -
-
so
60 75 100
(100) (120) (150) (200)
0011 PLLBypass
Notes: 1. Some PLL configurations may select bus, CPU, or PLL frequencies which are
not
useful, not
supported, or not tested for by the 604. For
complete
lnfonnation, see the 604 hardware
specifications for tlmilg comments. PLL frequencies (shown In parenthesis In the table above)
should
not
fall below 100 MHz,
and should not exceed 200 MHz.
2. In PLL-bypass mode, the SVSCLK i11>ut signal clocks the Internal processor directly, and the ·
b1M ls set for 1:1 mode operation. The PLL-bypass mode Is for test only,
and
Is
not
Intended for
functional use. In clock-off mode, no clocking occurs inside the 604 regardless of the SVSCLK
111)ut.
3. PLL_CFG(0:1) selects the CPU-to-bus ratio (1:1,1.5:1, 2:1, 3:1), PLL_CFG(2:3) selects the
CPU-to-PLL multiplier (x2, x4, x8).
7-32 PowerPC 604 RISC Microprocessor User's Manual