Checkstops; Reset Inputs; Powerpc 604 Microprocessor Configuration During Hreset - IBM PowerPC 604 User Manual

8.8.2 Checkstops
Tue 604 has two checkstop input signals-CKSTP _IN and
MCP
(when MSR[ME] is
cleared, and HIDO[EMCP] is set), and a checkstop output (CKSTP _OUT). If CKSTP _IN
or MCP is asserted, the 604 halts operations by gating off all internal clocks. The 604
asserts CKSTP_OUT if CKSTP_IN is asserted
If CKSTP _OUT is asserted by the 604, it has entered the checkstop state, and processing
has halted internally. The CKSTP _OUT signal can
be
asserted for various reasons
including receiving a TEA signal and detection of external parity errors. For more
information about checkstop state, see Section 4.5.2.2, "Checkstop State (MSR[ME]
=
0)."
8.8.3 Reset Inputs
The 604 has two reset inputs, described as follows:
• HRESET (hard reset)-The HRESET signal is used for power-on reset sequences,
or for situations in which the 604 must go through the entire cold-start sequence of
internal hardware initializations.
• SRESET (soft reset)-The soft reset input provides warm reset capability. This
input can be used
to
avoid forcing the 604 to complete the cold start sequence.
When either reset input is negated, the processor attempts
to
fetch code from the system
reset exception vector. The vector is located at off set OxOO 100 from the exception prefix (all
zeros or ones, depending on the setting of the exception prefix bit in the machine state
register (MSR[IP]). The IP bit is set for HRESET.
8.8.4 PowerPC 604 Microprocessor Configuration during HRESET
Tue 604's bus interface can
be
configured into one of two modes during a hard reset, as
described in Table 8-10.
Table 8-1
o.
PowerPC 604 Microprocessor Mode Configuration during HRESET
604Mode Input Signal Used
Timing Requirements Notes
Nonnal bus mode
mmw
Must be negated throughout the
duration
of
the
RRBET
assertion.
After~ negation, NmW
can be used normally.
Fast-L2/data streaming
mmw
Must be asserted and negated Can be implemented by
mode
coincidentally with~ and
tying
15RTRV
to
remain negated during normal
R'FIESET.
operation.
Chapter 8. System Interface Operation
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