Coherency And Secondary Caches; Page Table Control Bits; Mesi State Diagram - IBM PowerPC 604 User Manual

3.6.2 Coherency and Secondary Caches
The 604 supports the use of a larger secondary cache that can be implemented in different
configurations. The use of an L2 cache can serve to further improve performance by further
reducing the number of bus accesses. The L2 cache must operate with respect to the
memory system in a manner that is consistent with the intent of the Power PC architecture.
L2 caches must forward all relevant system bus traffic onto the 604 so the 604 can take the
appropriate actions to maintain memory coherency as defined by the PowerPC architecture.
3.6.3 Page Table Control Bits
The Power PC architecture allows certain memory characteristics to be set on a page and on
a block basis. These characteristics include the following:
• Write-back/write-through (using the W bit)
• Cacheable/noncacheable (using the I bit)
• Memory coherency enforced/not enforced (using the M bit)
An additional page control bit, G, handles guarded storage and is not considered here. This
ability allows both single- and multiple-processor system designs to exploit numerous
system-level performance optimizations.
The PowerPC architecture defines two of the possible eight decodings of these bits
to
be
unsupported (WIM = 110 or 111 ).
Note that software must exercise care with respect to the use of these bits if coherent
memory support is desired. Careless specification of these bits may create situations that
present coherency paradoxes to the processor. In particular, this can happen when the state
of these bits is changed without appropriate precautions (such as flushing the pages that
correspond to the changed bits from the caches of all processors in the system) or when the
address translations of aliased real addresses specify different values for any of the WIM
bits. These coherency paradoxes can occur within a single processor or across several
processors.
It is important to note that in the presence of a paradox, the operating system software is
responsible for correctness. The next section provides a few simple examples to convey the
meaning of a paradox.
3.6.4 MESI State Diagram
The 604 provides dedicated hardware to provide data cache coherency by snooping bus
transactions. The address retry capability of the 604 enforces the MESI protocol, as shown
in Figure 3-6. Figure 3-6 assumes that the WIM bits are set to 001; that is, write-back,
caching-not-inhibited, and memory coherency enforced.
Chapter 3. Cache and Bus Interface Unit Operation
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