Cache And Bus Interface Unit Operation - IBM PowerPC 604 User Manual

Chapter 3
Cache and Bus Interface Unit Operation
This chapter describes the organization of the 604 's on-chip cache system, the MESI cache
coherency protocol, special concerns for cache coherency in single- and multiple-processor
systems, cache control instructions, various cache operations, and the interaction between
the cache and the memory unit.
To minimize the number of bus accesses, the 604 contains separate 16-Kbyte, four-way set-
associative instruction and data caches and also provides support for secondary (L2)
caching. The cache block size is 32 bytes. The cache is designed to adhere
to
a write-back
policy, but the 604 allows control of cacheability, write policy, and memory coherency at
the page and block level, as defined by the PowerPC architecture. The caches use a least
recently used (LRU) replacement policy.
The 604 cache implementation has the following characteristics:
• Separate 16-Kbyte instruction and data caches (Harvard architecture)
• Instruction and data caches are four-way set associative.
• Caches implement an LRU replacement algorithm within each set.
• The cache directories are physically addressed. The physical (real) address tag is
stored in the cache directory.
• Both the instruction and data caches have 32-byte cache blocks. A cache block is the
block of memory that a coherency state describes, also referred to as a cache line.
• The coherency state bi
ts
for each block of the data cache allow encoding for all four
possible MESI states:
- Modified (Exclusive) (M)
- Exclusive (Unmodified) (E)
- Shared (S)
- Invalid (I)
Chapter 3. Cache and Bus Interface Unit Operation