Instruction Cache; Data Cache - IBM PowerPC 604 User Manual

PowerPC implementations can control the following memory access modes on a page or
block basis:
• Write-back/write-through mode
• Cache-inhibited mode
• Memory coherency
• Guarded memory (prevents access for speculative execution)
The caches implement an LRU replacement algorithm.
1.2.4.1 Instruction Cache
The 604's 16-Kbyte, four-way set associative instruction cache is physically indexed.
Within a single cycle, the instruction cache provides up to four instructions. Instruction
cache coherency is not maintained by hardware.
The PowerPC architecture defines a special set of instructions for managing the instruction
cache. The instruction cache can be invalidated entirely or on a cache-block basis. The
instruction cache can be disabled/enabled and invalidated by setting the HID0[16] and
HID0[20] bits, respectively. The instruction cache can be locked by setting HID0[18].
1.2.4.2 Data Cache
The 604's data cache is a 16-Kbyte, four-way set associative cache. It is a
physically-indexed, nonblocking, write-back cache with hardware support for reloading on
cache misses. Within one cycle, the data cache provides double-word access to the LSU.
The data cache tags are dual-ported, so the process of snooping does not affect other
transactions on the system interface. If a snoop hit occurs, the LSU is blocked internally for
one cycle to allow the eight-word block of data to be copied to the write-back buffer.
To ensure cache coherency, the 604 data cache supports the four-state MESI
(modified/exclusive/shared/invalid) protocol.
These four states indicate the state of the cache block as follows:
• Modified (M)-The cache block is modified with respect to system memory; that is,
data for this address is valid only in the cache and not in system memory.
• Exclusive (E)-This cache block holds valid data that is identical to the data at this
address in system memory. No other cache has this data.
• Shared (S)-This cache block holds valid data that is identical to this address in
system memory and at least one other caching device.
• Invalid (I)-This cache block does not hold valid data.
Like the instruction cache, the data cache can be invalidated all at once or on a per cache
block basis. The data cache can be disabled/enabled and invalidated by setting the
HIDO[l7] and HID0[21] bits, respectively. The data cache can be locked by setting
HID0[19].
Chapter 1. Overview
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