Page Address Translation Summary - IBM PowerPC 604 User Manual

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The OEA requires that a synchronization instruction be issued to guarantee completion of
a tlbie instruction across all processors of a system. The 604 implements the tlbsync
instruction which causes a TLBSYNC broadcast operation to appear on the bus as an
address-only transaction, distinct from a SYNC operation. It is this bus operation that
causes synchronization of snooped tlbie instructions. Multiple tlbie instructions can be
executed correctly with only one tlbsync instruction, following the last tlbie, to guarantee
all previous tlbie instructions have been performed globally.
When the TLBSYNC bus operation is detected by a snooping 604, the 604 asserts the
ARTRY snoop status if any operations based on an invalidated TLB are pending.
Software must ensure that instruction fetches or memory references to the virtual pages
specified by the tlbie have been completed prior to executing the tlbie instruction.
Other than the possible TLB miss on the next instruction prefetch, the tlbie does not affect
the instruction fetch operation-that is, the prefetch buff er is not purged and does not cause
these instructions to be refetched.
The tibia instruction is optional for an implementation if its effects can be achieved through
some other mechanism. As described above, the tlbie instruction can be used to invalidate
a particular index of the TLB based on EA[ 14-19]. With that concept in mind, a sequence
of 64 tlbie instructions followed by a single tlbsync instruction would cause all the 604
TLB structures to be invalidated (for EA[l4-19] = 0, 1, 2, ... , 63). Therefore the tibia
instruction is not implemented on the 604. Execution of a tibia instruction causes an illegal
instruction program exception.
The tlbie and tlbsync instructions are described in detail in Section 2.3.6.3.3, "Translation
Lookaside Buffer Management Instructions,.-(OEA)." For more information about how
other processors react to TLB operations broadcast on the system bus of a multiprocessing
system, see Section 3.9.6, "Cache Reaction to Specific Bus Operations."
5.4.4 Page Address Translation Summary
Figure 5-8 provides the detailed flow for the page address translation mechanism.
The figure includes the checking of the N bit in the segment descriptor and then expands
on the "TLB Hit" branch of Figure 5-6. The detailed flow for the "TLB Miss" branch of
Figure 5-6 is described in Section 5.4.5, "Page Table Search Operation." Note that as in the
case of block address translation, if the dcbz instruction is attempted to be executed either
in write-through mode or as cache-inhibited (W = 1orI=1), the alignment exception is
generated. The checking of memory protection violation conditions for page address
translation is described in Chapter 7, "Memory Management," in
The Programming
Environments Manual.
Chapter 5. Memory Management
5-27

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