Decode Stage; Dispatch Stage - IBM PowerPC 604 User Manual

The ·fetch unit keeps the instruction buffer (four-entry decode and four-entry dispatch
buffer) supplied with instructions for the dispatcher
to
process. Normally, the fetch unit
fetches instructions sequentially, even when the instruction buffer is full because space may
become available by the time the instruction cache supplies them. Instructions are fetched
from the instruction cache in groups of four along double-word boundaries. Instructions
can be fetched from only one cache block at a time, so if only two instructions remain in
the cache block, only two instructions are fetched. If fetching is sequential, then it resumes
at four instructions per clock from the next cache block.
The next address to be fetched is affected by several different conditions. Each stage offers
its own candidate for the next instruction
to
be fetched, and the latest stage has the highest
priority. As a block is prefetched, the branch target address cache (BTAC) and the branch
history table (BHT) are searched with the fetch address. If the fetch address is found in the
BTAC, it is the fetch stage candidate for being the next instruction address (as shown in
Section 6.4.4.1.1, "Timing Example-Branch Timing for a BTAC Hit"); otherwise, the
next sequential address is the candidate provided by the fetch stage.
The decode logic may indicate, based on the BHT or an unconditional branch decode, that
an earlier BTAC prediction was incorrect. The BPU can indicate that a previous branch
prediction, either from the BTAC or the decoder was incorrect and it can supply a new fetch
address. In this case, the contents of the instruction buffers are flushed. Exception logic
within the completion logic may indicate the need to vector to an exception handler
address. From these choices the exception has first priority, the branch unit has second
priority, the decode correction of a BTAC prediction has third priority, and the BTAC
prediction has the final priority for instruction prefetching.
6.2.1.1.2 Decode Stage
The decode stage handles all time-critical instruction decoding for instructions in the
instruction buffer. The decode stage contains a four-instruction buffer that shifts one or two
pairs of instructions into the dispatch buffer as space becomes available.
6.2.1.1.3 Dispatch Stage
The dispatch pipeline stage is responsible for non-time-critical decoding of instructions
supplied by the decode stage and for determining which of the instructions can be
dispatched in the current cycle. Also, the source operands of the instructions are read from
the appropriate register file and dispatched with the instruction to the execute stage. At the
end of the dispatch stage, the dispatched instructions and their operands are latched into
reservation stations or execution unit input latches.
Chapter 6. Instruction Timing
6-9