Decode/Dispatch Unit; Branch Processing Unit (Bpu); Completion Unit - IBM PowerPC 604 User Manual

1.2.1.2 Decode/Dispatch Unit
The decode/dispatch unit provides the logic for decoding instructions and issuing them to
the appropriate execution unit. The eight-entry instruction queue consists of two four-entry
queues-a decode queue (DEQ) and a dispatch queue (DISQ).
The decode logic decodes the four instructions in the decode queue. For many branch
instructions, these decoded instructions along with the bits in the BHT, are used during the
decode stage for branch correction.
The dispatch logic decodes the instructions in the DISQ for possible dispatch. The dispatch
logic resolves unconditional branch instructions and predicts conditional branch
instructions using the branch decode logic, the BHT, and values in the CTR.
The 512-entry BHT provides two bits per entry, indicating four levels of dynamic
prediction-strongly not-taken, not-taken, taken, and strongly taken. The history of a
branch's direction is maintained in these two bits. Each time a branch is taken the value is
incremented (with a maximum value of three meaning strongly-taken); when it is not taken,
the bit value is decremented (with a minimum value of zero meaning strongly not-taken).
If the current value predicts taken and the next branch is taken again, the BHT entry then
predicts strongly taken. If the next branch is not taken, the BHT then predicts taken.
The dispatch logic also allocates each instruction to the appropriate execution unit. A
reorder buffer (ROB) entry is allocated for each instruction, and dependency checking is
done between the instructions in the dispatch queue. The rename buffers are searched for
the operands as the operands are fetched from the register file. Operands that are written by
other instructions ahead of this one in the dispatch queue are given the tag of that
instruction's rename buffer; otherwise, the rename buffer or register file supplies either the
operand or a tag. As instructions are dispatched, the fetch unit is notified that the dispatch
queue can be updated with more instructions.
1.2.1.3 Branch Processing Unit (BPU)
The BPU is used for branch instructions and condition register logical operations. All
branches, including unconditional branches, are placed in a reservation station until
conditions are resolved and they can be executed. At that point, branch instructions are
executed in order-the completion unit is notified whether the prediction was correct.
The BPU. also executes condition register logical instructions, which flow through the
reservation station like the branch instructions.
1.2.1.4 Completion Unit
The completion unit retires executed instructions from the reorder buffer (ROB) in the
completion unit and updates register files and control registers. The completion unit
recognizes exception conditions and discards any operations being performed on
subsequent instructions in program order. The completion unit can quickly remove
instructions from a mispredicted branch, and the decode/dispatch unit begins dispatching
from the correct path.
Chapter 1. Overview
1-9