IBM PowerPC 604 User Manual page 349

• The TTO-TT3, TBST, and TSIZO-TSIZ2 signals are remapped to form an 8-bit
extended transfer code (XATC) which specifies a command and transfer size for the
transaction. The XATC field is driven and snooped by the 604 during direct-store
transactions.
• Only the data signals such as DHO-DH31 and DPO-DP3 are used. The lower half of
the data bus and parity is ignored.
• The sender that initiated the transaction must wait for a reply from the receiver bus
unit controller (BUC) before starting a new operation.
• The 604 does not burst direct-store transactions.All direct-store transactions
generated by the 604 are single-beat transactions of four bytes or less (single data
beat tenure per address tenure).
Direct-store transactions use separate arbitration for the split address and data buses and
define address-only and single-beat transactions. The address-retry vehicle is identical,
although there is no hardware coherency support for direct-store transactions. The ARTRY
signal is useful, however, for pacing 604 transactions, effectively indicating to the 604 that
the BUC is in a queue-full condition and cannot accept new data.
In addition to the 'extensions noted above, there are fundamental differences between
memory-mapped and direct-store operations. For example, only half of the 64-bit data path
is available for 604 direct-store transactions. This lowers the pin count for 1/0 interfaces
but generally results in substantially less bandwidth than memory-mapped accesses.
Additionally, load/store instructions that address direct-store segments cannot complete
successfully without an error-free reply from the addressed BUC. Because normal direct-
store accesses involve multiple 1/0 transactions (streaming), they are likely to be very long
latency instructions; therefore, direct-store operations usually stall 604 instruction issue.
Figure 8-22 shows a direct-store tenure. Note that the 1/0 device response is an address-
only bus transaction.
It should be noted that in the best case, the use of the 604 direct-store protocol degrades
performance and requires the addressed controllers to implement 604 bus master capability
to generate the reply transactions.
Chapter 8. System Interface Operation
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