Memory Control Instructions-Dea; Supervisor-Level Cache Management Instruction-(Oea); Segment Register Manipulation Instructions; Translation Lookaside Buffer Management Instruction - IBM PowerPC 604 User Manual

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For infonnation on SPR encodings (both user- and supervisor-level) see Chapter 8,
"Instruction Set," in The Programming Environments Manual. Note that there are
additional SPRs specific to each implementation; for implementation-specific SPRs, see
the user's manual for that particular processor.
2.3.6.3 Memory Control Instructions-CEA
Memory control instructions include the following types of instructions:
• Cache management instructions (supervisor-level and user-level)
• Segment register manipulation instructions
• Translation lookaside buffer management instructions
This section describes supervisor-level memory control instructions. See Section 2.7.3,
"Memory Control Instructions-VEA," for more information about user-level cache
management instructions.
2.3.6.3.1 Supervisor-Level Cache Management lnstruction-(OEA)
Table 2-44 lists the only supervisor-level cache management instruction.
Table 2-44. Cache Management Supervisor-Level Instruction
Name Mnemonic Operand Syntax Implementation Notes
Data deb I rA,rB The EA
is
computed, translated, and checked for protection
Cache
violations as defined in the OEA.
Block The 604 broadcasts the essence al the instruction onto the 604
Invalidate
bus (using the kill operation). In addition, if the addressed block
is present in the cache, the 604 marks this data as invalid
regardless of whether the data is clean or modified. Note that
this can have the effect of destroying modified data which
is
why the instruction
is
privileged and has store semantics with
respect to protection.
See Section 2.7.3.l, "User-Level Cache Instructions-VEA," for cache instructions that
provide user-level programs the ability to manage the on-chip caches. If the effective
address references a direct-store segment, the instruction is treated as a no-op. Note that any
cache control instruction that generates an effective address that corresponds to a
direct-store segment (segment descriptor[T]
=
1) is treated as a no-op.
2-54 PowerPC 604 RISC Microprocessor User's Manual