IBM PowerPC 604 User Manual page 15

Paragraph
Number
7.2.9.3
7.2.9.4
7.2.9.5
7.2.9.6
7.2.9.6.l
7.2.9.6.2
7.2.10
7.2.10.1
7.2.10.2
7.2.10.3
7.2.10.4
7.2.10.5
7.2.11
7.2.12
7.2.12.1
7.2.12.2
7.2.12.3
7.2.12.4
8.1
8.1.1
8.1.2
8.1.3
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.3.2.1
8.3.2.2
8.3.2.2.1
8.3.2.2.2
8.3.2.3
8.3.2.4
8.3.2.4.1
8.3.2.5
8.3.3
8.4
8.4.1
xii
CONTENTS
Page
Number
Tltle
Machine Check Interrupt (MCP}-lnput .................................................... 7-25
Checkstop Input(CKSTP _IN}-lnput ....................................................... 7-26
Checkstop Output (CKSTP _OUT)-Output. ............................................ 7-26
Reset Signals ....................................•.....•..••............................................... 7-27
Hard Reset (HRESET}-Input .............................................................. 7-27
Soft Reset (SRESET}-lnput ................................................................ 7-27
Processor Configuration Signals .................................................................... 7-28
Timebase Enable (TBEN}-lnput ............................................................. 7-28
Reservation (RSRV}-Output ................................................................... 7-28
L2 Intervention (L2_1NT}-Input ...............•............................................. 7-28
Run (RUN}-lnput .................................................................................... 7-29
Halted (HALTED)---Output ..................................................................... 7-29
COP/Scan Interface ..................................................................•..................... 7-29
Clock Signals ................................................................................................. 7-30
System Clock (SYSCLK}-lnput. ............................................................. 7-30
Test Clock (CLK_OUT)-Output ............................................................. 7-31
Analog VDD (A VDD}-lnput .........................................•........................ 7-31
PLL Configuration (PLL_CFGO-PLL_CFG3}-Input .•.•.•......................• 7-31
Chapter 8
System Interface Operation
PowerPC 604 Microprocessor System Interface Overview .........•....................... 8-1
Operation of the Instruction and Data Caches ................................................. 8-2
Operation of the System Interface .......................•••.•............••......................... 8-4
Direct-Store Accesses ...................................................................................... 8-5
Memory Access Protocol ..................................................................................... 8-6
Arbitration Signals ........................................................................................... 8-7
Address Pipelining and Split-Bus Transactions ............................................... 8-9
Address Bus Tenure ........................................................................................... 8-10
Address Bus Arbitration .........................••.•................................................... 8-10
Address Transfer ............................................................................................ 8-12
Address Bus Parity ............•.••••........................................••........................ 8-13
Address Transfer Attribute Signals ........................................................... 8-13
Transfer Type (TTO-TT4) Signals ........................................................ 8-13
Transfer Size (TSIZO-TSIZ2) Signals ................................................... 8-13
Burst Ordering During Data Transfers ...................................................... 8-14
Effect of Alignment in Data Transfers ...................................................... 8-14
Alignment of External Control Instructions .......................................... 8-16
Transfer Code (TCO-TC2) Signals ............................................................ 8-17
Address Transfer Termination ...................................................................... 8-18
Data Bus Tenure ................................................................................................ 8-20
Data Bus Arbitration ...................................................................................... 8-20
PowerPC 604 Rl~IC Microproceasor
User'•
Manual