Timing Example-Branch With Btac Miss/Dispatch Correction; Timing Example-Branch With Btac Miss/Execute Correction - IBM PowerPC 604 User Manual

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6.4.4.1.3 Timing Example-Branch with BTAC Miss/Dispatch Correction
Figure 6-11 uses the same code sequence as the example shown in Figure 6-9, and shows
the timing when the BTAC miss is corrected in the dispatch stage. The timing in this
example is identical to that in Figure 6-10, except that the timings for instructions 4-7 are
shifted over by one cycle.
0
•••
Oand
1 Id
2add
3bc
I I
I I
I I
I I
I I
_l_ J_
C:::J
Fetch
I ::
?t i
Decode
e:::::::I _
Dispatch
2
3
4
or
l
_l_
111111
Execute
IIIIIII1
Complete
- Write-Back
4 5 6 7 8
I
I
I
I
I
I
I
I
I
•
•• • 1111 •.
Figure 6-11. Instruction Timing-Branch with BTAC Miss/Dispatch Correction
6.4.4.1.4 Timing Example-Branch with BTAC Miss/Execute Correction
Figure 6-12 uses the same code sequence as the previous examples, and shows the timing
when the BTAC miss is corrected in the execute stage. The timing in this example is
identical to that in Figure 6-10, except that the timings for instructions 4-7 are shifted over
by two cycles (and
ov~r
one cycle when compared to the timing when correction is
provided in the dispatch stage, as shown in Figure 6-11).
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PowerPC 604
RISC
Microprocessor User's Manual