IBM PowerPC 604 User Manual page 46

Address Bus
Address Arbitration
Address Transfer Start
Address Transfer
Transfer Attrbute
Address Transfer Termination
Clocks
~
~
~
--
PowerPC604
--
Processor
--
I
=
+3.3V -
Figure 1-4. System Interface
....
Data Bus
Data Arbitration
Data Transfer
Data
Transfer Tenninatlon
Processor State
System Status
Test/Control/Miscellaneous
Four-beat burst-read memory operations that load an eight-word cache block into one of
the on-chip caches are the most common bus ttansactions in typical systems, followed by
burst-write memory operations, direct-store operations, and single-beat (noncacheable or
write-through) memory read and write operations. Additionally, there can be address-only
operations, variants of the burst and single-beat operations (global memory operations that
are snooped and atomic memory operations, for example), and address retty activity (for
example, when a snooped read access hits a modified line in the
data
cache).
The BIU implements the critical double-word first access where the double-word requested
by the fetcher or the load/store unit is fetched first and the remaining words in the line are
fetched later. The critical double-word as well as other words in the cache block are
forwarded to the fetcher or to the LSU before they are written to the cache.
Memory accesses can occur in single-beat or four-beat burst
data
ttansfers. The address and
data
buses are independent for memory accesses to support pipelining and split
ttansactions. The 604 supports bus pipelining and out-of-order split-bus ttansactions. In
general, the bus-pipelining mechanism allows as many as three address tenures to be
outstanding before a
data
tenure is initiated. Address tenures for address-only ttansactions
can exceed this limit.
Typically, memory accesses are weakly-ordered. Sequences of operations, including
load/store stting/multiple insttuctions, do not necessarily complete in the same order in
which they began-maximizing the efficiency of the bus without sacrificing coherency of
the
data.
The 604 allows load operations to precede store operations (except when a
dependency exists, of course). In addition, the 604 provides a separate queue for snoop
push operations so these operations can access the bus ahead of previously queued
operations. The 604 dynamically optimizes run-time ordering of load/store ttaffic to
improve overall performance.
Chapt• 1. OVervlew
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