IBM PowerPC 604 User Manual page 63

Table 1-2. Overview of Exceptions and Conditions (Continued)
Exception
Vector Offset
Causing Conditions
Type
(hex)
Program 00700
A program exception is caused by one al the following exception conditions,
which correspond to bit settings in SRR1 and arise during execution of an
instruction:
.
Floating-point exceptions-A floating-point enabled exception condition
causes an exception when FPSCR[FEX) is
set
and depends on the values
in MSR(FEO) and MSR[FE1].
FPSCR[FEX] is set by the execution of a floating-point instruction that
causes an enabled exception or
by
the execution al a •move to FPSCR"
lnstruetion that results in both an exception condition bit and its
corresponding enable bit being set in the FPSCR.
.
Illegal instruction-An illegal instruction program exception is generated
when execution of an instruction is attempted with an illegal opcode or iUegal
combination al opcode and extended opcode fields or when execution of an
optional instruction not provided in the specific implementation
is
attempted
(these do not include those optional instructions that are treated as no-ops).
.
Privileged instruetion-A privileged instruetion type program exception is
generated when the execution of a privileged instruction Is attempted and
the MSR user privilege bit, MSR[PR),
is
set. This exception
is
also
generated for mtspr or mfspr with an invalid SPR field If SPR[O) = 1 and
MSR[PR]= 1.
.
Trap-A trap type program exception is generated when any of the
conditions specified in a trap instruction is met.
Floating-point 00800 A floating-point unavailable exception Is caused by an attempt to execute a
unavailable
floating-point instruction (induding floating-point load, store, and move
instructions) when the floating-point available bit
is
disabled (MSR[FP) = O).
Decrementer
00900
The decrementer exception occurs when the most significant bit of the
decrementer (DEC) register transitions from O to 1.
Reserved OOAOO-OOBFF
-
System can
oocoo
A system call exception occurs when a System Call (sc) instruction
is
executed.
Trace
00000 Either MSR[SE] = 1 and any lnstruetion (except rfl) successfully completed or
MSR[BE] = 1 and a branch instruction
is
completed.
Floating-point OOEOO Defined by the PowerPC architecture, but not required in the 604.
assist
Reserved OOE10-00EFF
-
Performance OOFOO The performance monitoring interrupt is a 604-specilic exception and
is
used
monitoring
with
the 604 performance monitor, described in Section 1.5, "Performance
interrupt
Monitor."
The performance monitoring facility can be enabled to signal an exception
when the value In one of the performance monitor counter registers (PMC1 or
PMC2) goes negative. The conditions that can cause this exception can be
enabled or disabled in the monitor mode control register O (MMCRO).
Although the exception condition may occur when the MSR EE bit is deared,
the actual interrupt
is
masked
by
the EE bit and cannot be taken until the EE bit
Is
set.
Reserved
01000--012FF
-
1-32 PowerPC 604 RISC Microprocessor User's Manual