Instruction Timing Overview - IBM PowerPC 604 User Manual

• Rename buffer-Temporary buffers used by instructions that have not completed
and as write-back buffers for those that have:
• Finish-The term indicates the final cycle of execution. In this cycle, the completion
buffer is updated to indicate that the instruction has finished executing.
• Completion----Completion occurs when an instruction is removed from the
completion buffer. When an instruction completes we can be sure that this
instruction and all previous instructions will cause no exceptions. In some situations,
an instruction can finish and complete in the same cycle.
• Write-back-Write-back (in the context of instruction handling) occurs when a
result is written from the rename registers into the architectural registers (typically
the GPRs and FPRs). Results are written back at completion time or are moved into
the write-back buffer. Results.in the write-back buffer cannot be flushed.Han
exception occurs, these buffers must write back before the exception is taken.
6.2 Instruction Timing Overview
The 604 has been designed to maximize instruction throughput and
minimize
average
instruction execution latency. For many of the instructions in the 604, this can be simplified
to include only the execute phase for a particular instruction. Note that the number of
additional cycles required by data access instructions depends on whether the access hits in
the cache in which case there is a single cycle required for the cache access;
If
the access
misses in the cache, the number of additional cycles required is affected by the processor-
to-bus clock ratios and other factors pertaining to memory access.
In keeping with this definition, most integer instructions have a latency of one clock cycle
(for example, results for these instructions are ready for use on the next clock cycle after
issue). Other instructions, such as the integer multiply, require more than one clock cycle
to finish execution.
Figure 6-1 provides a detailed block diagram-showing the additional data paths that
contribute to the improved efficiency in instruction execution and more clearly shows the
relationships between execution units and their associated register files.
Chapter &. Instruction Timing
6-3