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5.5 Direct-Store Interface Address Translation
As described for memory segments, all accesses generated by the processor map to a
segment descriptor in the segment table.
If
T
=
1 for the selected segment descriptor and
there are no BAT hits, the access maps to the direct-store interface, invoking a specific bus
protocol for accessing some special-purpose 1/0 devices. Direct-store segments are
provided for POWER compatibility. As the direct-store interface is present only for
compatibility with existing 1/0 devices that used this interface and the direct-store interface
protocol is not optimized for performance, its use is discouraged. Applications that require
low latency load/store access to external address space should use memory-mapped 1/0,
rather than the direct-store interface.
5.5.1 Direct-Store Interface Accesses
When the address translation process determines that the segment descriptor has T = 1,
direct-store interface address translation is selected and no reference is made to the page
tables and referenced and changed bits are not updated. These accesses are performed as
if
the WIMG bits were Ob0101; that is, caching is inhibited, the accesses bypass the cache,
hardware-enforced coherency is not required, and the accesses are considered guarded.
The specific protocol invoked to perform these accesses involves the transfer of address and
data information in packets; however, the PowerPC OEA does not define the exact
hardware protocol used for direct-store interface accesses. Some instructions cause
multiple address/data transactions
to
occur on the bus.
In
this case, the address for each
transaction is handled individually with respect to the DMMU.
The following data is sent by the 604 to the memory controller in the protocol (two packets
consisting of address-only cycles) described in Section 8.6, "Direct-Store Operation."
• PacketO
- One of the Kx bits (Ks or Kp) is selected to
be
the key as follows:
- For supervisor accesses (MSR[PR]
=
0), the Ks bit is used and Kp is ignored.
- For user accesses (MSR[PR]
=
1), the Kp bit is used and Ks is ignored.
- The contents of bits 3-31 of the segment register, which is the BUID field
concatenated with the "controller-specific" field.
• Packet 1-SR[28-31] concatenated with the 28 lower-order bits of the effective
address, EA4-EA31.
5.5.2 Direct-Store Segment Protection
Page-level memory protection as described in Section 5.4.2, "Page Memory Protection," is
not provided for direct-store segments. The appropriate key bit (Ks or Kp) from the
segment descriptor is sent to the memory controller,
and
the memory controller implements
any protection required. Frequently, no such mechanism is provided; the fact that a
direct-store segment is mapped into the address space of a process may
be
regarded as
sufficient authority to access the segment.
Chapter 5. Memory Management
5-35
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