IBM PowerPC 604 User Manual page 71

registers, while other SPRs may be more typically accessed as the side effect of
executing other instructions.
- Integer exception register (XER). The XER indicates overflow and carries for
integer operations. It is set implicitly by many instructions. See "XER Register
(XER)," in Chapter 2, "PowerPC Register Set," of The Programming
Environments Manual for more information.
- Link register (LR). The LR provides the branch target address for the Branch
Conditional
to
Link Register (bclrx) instruction, and can optionally be used to
hold the logical address of the instruction that follows a branch and link
instruction, typically used for linking
to
subroutines. For more information, see
"Link Register (LR)," in Chapter 2, "PowerPC Register Set," of The
Programming Environments Manual.
- Count register (CTR). The CTR holds a loop count that can be decremented
during execution of appropriately coded branch instructions. The CTR can also
provide the branch target address for the Branch Conditional to Count Register
(bcctrx) instruction. For more information, see "Count Register (CTR)," in
Chapter 2, "PowerPC Register Set," of The Programming Environments
Manual.
• User-level registers (VEA)-The PowerPC VEA introduces the time base facility
(TB), a 64-bit structure that maintains and operates an interval timer. The TB
consists of two 32-bit registers-time base upper (TBU) and time base lower (TBL).
Note that the time base registers can be accessed by both user- and supervisor-level
instructions. In the context of the VEA, user-level applications are permitted
read-only access to the TB. The OEA defines supervisor-level access
to
the TB for
writing values to the TB. For more information, see "PowerPC VEA Register
Set-Time Base," in Chapter 2, "PowerPC Register Set," of The Programming
Environments Manual.
• Supervisor-level registers (OEA)-The OEA defines the registers that are used
typically by an operating system for such operations as memory management,
configuration, and exception handling. The supervisor-level registers defined by
the
PowerPC architecture for 32-bit implementations are describes as follows:
- Configuration registers
- Machine state register (MSR). The MSR defines the state of the processor.
The MSR can be modified by the Move to Machine State Register (mtmsr),
System Call (sc), and Return from Exception (rfi) instructions. It can be read
by the Move from Machine State Register (mfmsr) instruction. See "Machine
State Register (MSR)," in Chapter 2, "PowerPC Register Set," of The
Programming Environments Manual for more information.
Chapter 2. PowerPC 604 Processor Programming Model 2-5
-