IBM PowerPC 604 User Manual page 206

Table 5-3. Translatlon Exception COndltlons
Condition Deacrlptlon
Exception
Page fault (no PTE found) No matching PTE found in page tables (and no
I access: ISi exception
matching BAT array entry) SRR1[1) = 1
0 access: OSI exception
OSISR[1] =1
Block protection violation
Conditions descri>ed for block In "Block Memory I access: ISi exception
Protection"
in
Chapter7, "Memory Management,"
SRR1[4]= 1
in The Programming Environments Manual."
O access: OSI exception
OSISR[4]=1
Page protection violation Conditions descri>ed for page in "Block Memory I access: ISi exception
Protection"
In
Chapter7, "Memory Management," SRR1[4]= 1
in
The
Programming Environments Manual.
0 access: OSI exception
DSISR[4]=1
No-execute protection Attempt to fetch instruction when SR[NJ = 1 ISi exception
violation SRR1[3) = 1
Instruction fetch from Attempt to fetch instruction when SR(T) = 1 ISi exception
direct-store segment SRR1[3) =1
Instruction fetch from Attempt to fetch Instruction when MSR[IR] = 1 and ISi exception
guarded memory either matching xBAT[G] = 1, or no matching BAT SRR1[3) =1
entry and PTE[G] = 1
In addition to the translation exceptions, there are other MMU-related conditions (some of
them defined as implementation-specific and therefore, not required by the architecture)
that can cause an exception to occur. These exception conditions map to the processor
exception as shown in Table 5-4. The only MMU exception conditions that occur when
MSR[DR] = 0 are the conditions that cause the alignment exception for data accesses. For
more detailed information about the conditions that cause the alignment exception (in
particular for string/multiple instructions), see Section 4.5.6, "Alignment Exception
(Ox00600)."
Note that some exception conditions depend upon whether the memory area is set up as
write-though
CH
= 1) or cache-inhibited (I = 1). These bits are described fully in
"Memory/Cache Access Attributes," in Chapter 5, "Cache Model and Memory
Coherency," of
The Programming Environments Manual.
Refer to Chapter 4,
"Exceptions," and to Chapter 6, "Exceptions," in
The Programming Environments Manual
for a complete description of the SRRl and DSISR bit settings for these exceptions.
Chapter 5. Memory Management
5-17