Speculative Execution - IBM PowerPC 604 User Manual

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Figure 6-12. Instruction Timing-Branch with BTAC Miss/Execute Correction
6.4.5 Speculative Execution
To take fullest advantage of pipelining and parallelism, the 604 speculatively executes
instructions along a predicted path until the branch is resolved. The 604 can handle as many
as four dispatched, uncompleted branch instructions (with four more in the instruction
queue) and can execute instructions from the predicted path of two unresolved branch
instructions. The results of speculatively executed instructions (the predicted state) are kept
in temporary locations, such as rename buffers, the completion buffer, and various shadow
registers. Architecturally defined resources are updated only after a branch is resolved.
To record the predicted state, the 604 uses many of the same resources (primarily the
rename buffers and completion buffer) and logic as the mechanism used to maintain a
precise exception model, as is common among superscalar implementations. The 604
design avoids the performance degradation that may come from such a design due to
speculative execution of longer latency instructions, by implementing additional logic to
record the predicted state whenever a predicted branch instruction is dispatched. This
allows the state to be quickly recovered when the branch prediction is incorrect. The
recording of these predicted states makes it possible to identify and selectively remove
instructions from the rnispredicted path.
A shadow register is used with the CTR and LR to accelerate instructions that access these
registers. Shadow registers are updated and the old value is saved whenever a branch
instruction is dispatched, even if it is from a predicted path for a branch that has not yet been
Chapter 6. Instruction Timing 6-29