Address Transfer Termination - IBM PowerPC 604 User Manual

Table 8-6. Transfer COde Encoding (Continued}
TT
Type
Code
WT
TCO TC1 TC2 Operation
Kill block 1 0 0
0
Kill block and allocate, no cast
out required (dcbz)
Kill block 1 0 0 1 Kill block and aUocate,
cast
out required (dcbz)
KiUblock 1 0 0
0
Kill block, write to shared
block
Read
1
w3
0
x
0 Data read, cast
out
required
Read
w3
0 x 1 Data read, cast
out
required
Read
w3
1
x
0 Instruction read
Instruction cache x 1
0 0 KiU block de-aRocate
block invalidate (lcbl)
2
Note: 1. Read encompasses all of the read or read-with-intent-to-modify operations,
both
normal and atomic.
2. The lcbl instruction is distinguished from kill block by assertion of the TI4 bit.
3. Value determined by write-through bit from translation.
8.3.3 Address Transfer Termination
The address tenure of a bus operation is tenninated when completed with the assertion of
AACK, or retried with the assertion of ARTRY. The SHD signal may also be asserted either
coincident with the ARTRY signal, or alone to indicate that a copy of the requested data
exists in one of the devices on the bus, and that the requesting device should mark the data
as shared in its cache. The 604 does not terminate the address transfer until the AACK
(address acknowledge) input is asserted; therefore, the system can extend the address
transfer phase by delaying the assertion of AACK to the 604. AACK can be asserted as
early as the bus clock cycle following TS (see Figure 8-7), which allows a minimum
address tenure of two bus cycles. As shown in Figure 8-7, these signals are asserted for one
bus clock cycle, three-stated for half of the next bus clock cycle, driven high till the
following bus cycle, and finally three-stated. Note that AACK must be asserted for only one
bus clock cycle.
The address transfer can be terminated with the requirement to retry if ARTRY is asserted
anytime during the address tenure and through the cycle following AACK. The assertion
causes the entire transaction (address and data tenure) to be rerun. As a snooping device,
the 604 asserts ARTRY for a snooped transaction that hits modified data in the data cache
that must be written back to memory, or if the snooped transaction could not be serviced.
As a bus master, the 604 responds to an assertion of ARTRY by aborting the bus transaction
and re-requesting the bus. Note that after recognizing an assertion of ARTRY and aborting
the transaction in progress, the 604 is not guaranteed to run the same transaction the next
time it is granted the bus.
8-18
PowerPC 604 RISC Micropr0C8880r User's Manual