Page Table Search Operation - IBM PowerPC 604 User Manual

5.4.5 Page Table Search Operation
H the translation is not found in the TLBs (a TLB miss), the 604 initiates a table search
operation which is described in this section. Formats for the PTE are given in "PTE Format
for 32-Bit Implementations," in Chapter 7, "Memory Management," of
The Programming
Environments Manual.
The following is a summary of the page table search process performed by the 604:
1. The 32-bit physical address of the primary PTEG is generated as described in "Page
Table Addresses" in Chapter 7, "Memory Management," of
The Programming
Environments Manual.
2. The first PTE (PTEO) in the primary PTEG is read from memory. PTE reads should
occur with an implied WIM memory/cache mode control bit setting of ObOOl.
Therefore, they are considered cacheable and read (burst) from memory and placed
in the cache.
3. The PTE in the selected PTEG is tested for a match with the virtual page number
(VPN) of the access. The VPN is the VSID concatenated with the page index field
of the virtual address. For a match to occur, the following must be true:
- PTE[H] =0
- PTE[V]
=
1
- PTE[VSID]
=
VA[0-23]
- PTE[API] = VA[24-29]
4.
If
a match is not found, step 3 is repeated for each of the other seven PTEs in the
primary PTEG.
If
a match is found, the table search process continues as described
in step 8. If a match is not found within the 8 PTEs of the primary PTEG, the address
of the secondary PTEG is generated.
5. The first PTE (PTEO) in the secondary PTEG is read from memory. Again, because
PTE reads typically have a WIM bit combination of ObOOl, an entire cache line is
read into the on-chip cache.
6. The PTE in the selected secondary PTEG is tested for a match with the virtual page
number (VPN) of the access. For a match to occur, the following must be true:
- PTE[H] = 1
- PTE[V]
=
1
- PTE[VSID] = VA[0-23]
- PTE[API]
=
VA[24-29]
7. If a match is not found, step 6 is repeated for each of the other seven PTEs in the
secondary PTEG. If it is never found, an exception is taken (step 9).
8. If a match is found, the PTE is written into the on-chip TLB and the R bit is updated
in the PTE in memory (if necessary). If there is no memory protection violation, the
C bit is also updated in memory (if the access is a write operation) and the table
search is complete.
Chapter
s.
Memory Management 5-29