IBM PowerPC 604 User Manual page 325

example, Table 8-4 shows that one-byte data is always aligned; however, for a four-byte
word to be aligned, it must be oriented on an address that is a multiple of four.
Table 8-4. Aligned Data Transfers
Data Bus Byte Lane(s)
Transfer Size TSIZO TSIZ1 TSIZ2 A29-A31
0
1
2
3 4 5 6 7
·Byte
0 0 1 000
-./
-
-
- -
-
-
-
0 0 1 001
-
-./
-
-
-
- -
-
0
0 1
010
-
-
-./
-
- -
-
-
0 0 1 011
- - -
-./
-
-
-
-
0 0
1
100
-
- - -
-./
-
-
-
0 0
1 101
-
-
-
-
-
-./
- -
0 0 1 110
-
- -
-
- -
-./
-
0
0 1 111
- -
- - - - - -./
HaHword
0 1 0 000
-./
-./
- -
-
-
-
-
0 1 0 010
-
-
-./
-./
- - -
-
0 1 0 100
-
-
-
-
-./
-./
-
-
0
1 0
110
-
- -
-
-
-
-./ -./
Word
1 0 0 000
-./ -./ -./ -./
-
-
-
-
1
0 0
100
-
-
-
-
-./
-./ -./ -./
Double word
0 0 0 000
-./
-./ -./ -./
-./ -./
-./ -./
The 604 supports misaligned memory operations, although their use may substantially
degrade performance. Misaligned memory transfers address memory that is not aligned to
the size of the data being transferred (such as, a word read of an odd byte address).
Although most of these operations hit in the primary cache (or generate burst memory
operations if they miss), the 604 interface supports misaligned transfers within a word (32-
bit aligned) boundary, as shown in Table 8-5. Note that the four-byte transfer in Table 8-5
is only one example of misalignment. As long as the attempted transfer does not cross a
word boundary, the 604 can transfer the data on the misaligned address (for example, a half-
word read from an odd byte-aligned address). An attempt to address data that crosses a
word boundary requires two bus transfers
to
access the data.
Due to the performance degradations associated with misaligned memory operations, they
are best avoided. In addition to the double-word straddle boundary condition, the address
translation logic can generate substantial exception overhead when the load/store multiple
and load/store string instructions access misaligned data. It is strongly recommended that
software attempt
to
align code and data where possible.
Chapter 8. System Interface Operation
8-15