IBM PowerPC 604 User Manual page 199

-
0 31
Address Translation Disabled
Segment
Descriptor
Located
fr= 1) (T=O)
0
Page Address
Translation
Effective Address
51
Virtual Address
Direct-store Segment
Translation
(see Section 5.5)
Look Up in
Page Table
(MSR[IR]
=
0,
or
MSR[DR]
=
0)
Match with BAT
Registers
Block Address
Translation
(see Section 5.3)
Real Addressing Mode
Effective Address • Physical Address
(see Sedion
52)
~o
__
__...._~~~-3~1 ~o~~~~,..._~....,31 ~o---~_._~~~....,31 ~o~~....&.-~~~"""'31
Direct-store Address Physical Address Physical Address Physical Address
Figure 5-4. Address Translation Types
Direct-store address translation is used when the direct-store translation control bit (T bit)
in the corresponding segment descriptor is set. In this case, the remaining information in
the segment descriptor is interpreted as identifier information that is used with the
remaining effective address bits to generate the packets used in a direct-store interface
access on the external interface; additionally, no TLB lookup or page table search is
performed.
Translation is disabled for real addressing mode. In this case the physical address generated
is identical to the effective address. Instruction and data address translation is enabled with
the MSR[IR] and MSR[DR] bits, respectively. Thus when the processor generates an
access, and the corresponding address translation enable bit in MSR (MSR[IR] for
instruction accesses and MSR[DR] for data accesses) is cleared, the resulting physical
address is identical to the effective address and all other translation mechanisms are
ignored.
5-10
PowerPC 604 RISC Microprocessor User's Manual