Address Transfer Start Signals; Transfer Start (Ts); Transfer Start {Ts)-Output; Extended Address Transfer Start (Xats) - IBM PowerPC 604 User Manual

7 .2.2 Address Transfer Start Signals
Address transfer start signals are input and output signals that indicate that an address bus
transfer has begun. The transfer start (TS) signal identifies the operation as a memory
transaction; extended address transfer start (XATS) identifies the transaction as a direct-
store operation.
For detailed information about how TS and XATS interact with other signals, refer to
Section 8.3.2, "Address Transfer," and Section 8.6, "Direct-Store Operation," respectively.
7 .2.2.1 Transfer Start (TS)
The TS signal is both an input and an output signal on the 604.
7 .2.2.1.1 Transfer Start {TS)-Output
Following are the state meaning and timing comments for the TS output signal.
State Meaning
Asserted-Indicates that the 604 has begun a memory bus
transaction and that the address-bus and transfer-attribute signals are
valid. When asserted with the appropriate TTO-TT4 signals it is also
an implied data bus request for a memory transaction (unless it is an
address-only operation).
Negated-Is negated during a direct-store operation.
Timing Comments
Assertion-Coincides with the assertion of ABB.
Negation-Occurs one bus clock cycle after TS is asserted.
High Impedance-Occurs one bus clock cycle after TS is negated.
7 .2.2.1.2 Transfer Start {TS)-lnput
Following are the state meaning and timing comments for the TS input signal.
State Meaning
Asserted-Indicates that another master
has
begun a bus transaction
and that the address bus and transfer attribute signals are valid for
snooping (see GBL).
Negated-Indicates that no bus transaction is occurring.
Timing Comments
Assertion-May occur during the assertion of ABB.
Negation-Must occur one bus clock cycle after TS is asserted
7 .2.2.2 Extended Address Transfer Start (XATS)
The XATS signal is both an input and an output signal on the 604.
7 .2.2.2.1 Extended Address Transfer Start (XATS)-Output
Following are the state meaning and timing comments for the XATS output signal.
State Meaning
Asserted-Indicates that the 604 has begun a direct-store operation
and that the first address cycle is valid When asserted with the
appropriate XATC signals it is also an implied data bus request for
certain direct-store operation (unless it is an address-only operation).
Negated-Is negated during an entire memory transaction.
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PowerPC 604 RISC Microprocessor User's Manual