Move To/From Special-Purpose Register Instructions (Uisa); Memory Synchronization Lnstructions-Uisa - IBM PowerPC 604 User Manual

Because
mtcrf
instructions that update a single field do not require such synchronization
that other
mtcrf
instructions do, and because two such single-field instructions can execute
in parallel, it is typically more efficient to use multiple
mtcrf
instructions that update only
one field apiece than
to
use one
mtcrf
instruction that updates multiple fields. A rule of
thumb follows:
• It is always
more efficient to use two
mtcrf
instructions that update only one field
apiece than
to
use one
mtcrf
instruction that updates two fields.
- It is
almost always
more efficient to use three or four
mtcrf
instructions that
update only one field apiece than
to
use one
mtcrf
instruction that updates three
fields.
- It is
often
more efficient to use more than four
mtcrf
instructions that update only
one field than to use one
mtcrf
instruction that updates four fields.
2.3.4.6.2 Move to/from Special-Purpose Register Instructions (UISA)
Table 2-34 lists the
mtspr
and
mfspr
instructions.
Table 2-34. Move to/from Speclal-Purpose Register Instructions (UISA)
Name Mnemonic Op•and Syntax
Move to Special Purpose Register mtspr SPR,rS
Move from Special Purpose Register
mfspr
rD,SPR
2.3.4.7 Memory Synchronization lnstructions-UISA
Memory synchronization instructions control the order in which memory operations are
completed with respect to asynchronous events, and the order in which memory operations
are seen by other processors or memory access mechanisms. See Chapter 3, "Cache and
Bus Interface Unit Operation," for additional information about these instructions
and
about related aspects of memory synchronization.
Table 2-35. Memory Synchronization lnstructlons-UISA
Name Mnemonic Operand Syntax
Load Word and Reserve Indexed lwarx rD,rA,rB
Store Word Conditional Indexed stwcx. rS,rA,rB
Synchronize sync
-
The proper paired use of the lwarx with
stwcx.
instructions allows programmers
to
emulate
common semaphore operations such as "test and set," "compare and swap," "exchange
memory," and "fetch
and add."
The lwarx instruction must
be
paired with an stwcx.
instruction with the same effective address used for both instructions of the pair. Note that
the reservation granularity is implementation-dependent. See 2.3.5.2, "Memory
Synchronization Instructions-VEA," for details about additional memory
synchronization (eieio and isync) instructions.
Chapter 2. PowerPC 604 Processor Programming Model
2·47
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