User-Level Cache Instructions - IBM PowerPC 604 User Manual

Table 2·38. User-Level cache Instructions
Name Mnemonic
Op•and
Implementation Notes
Syntax
Data debt rA,rB The VEA defines this instruction to
aDow
for potential system
Cache performance enhancements through the use al software-initiated
Block Touch
pref etch hints. Implementations are
not
required to take any action based
-
off the execution of this lnstNctlon,
but
they may choose to prefetch the
cache block corresponding to the effective address Into their cache. The
604 performs the prefetch when the address hits in the TLB or the BAT, is
permitted load access from the addressed page, Is not directed to a
direct-store segment, and is directed at a cacheable page. If the
operation does not meet these criteria,
It
is treated as a no-op. The data
brought into the cache as a result of this instNction is validated
In
the
same way a load instNction would be (that is, if no dher bus
participant
has a copy, it is marked as Exclusive, otherwise it is marked as Shared).
The memory reference ol a debt causes the reference bit to be set.
A successful debt instNction affects the state
of the TLB and cache LRU
bits as defined by the LRU algorithm.
Data deb tat rA,rB
This instNctions behaves Uke the debt lnstNction.
Cache
Block
Touch for
Store
Data dcbz
rA,rB
The effective address is computed, translated, and checked for
Cache
protection violations as defined In the VEA. If the 604 does not
have
Block Set exclusive access to the block,
It
presents an operation
onto
the 604 bus
to Zero
Interface that instNcts all other processors to invalidate copies of the
block that may reside in their cache (this Is the kiU operation on the bus).
After it has exclusive access, the 604 writes all zeros Into the cache
block. If the 604 already has exclusive access, it immediately writes all
zeros Into the cache block. H the addressed block is within a
noncacheable or a write-through page, or If the cache
is locked or
disabled, the an aHgnment exception occurs.
If the operation is successful, the cache block is marked modified.
Data dcbat rA,rB The effective address is computed, translated, and checked tor
Cache prdectlon violations as defined In the VEA. If the 604 does not have
Block Store exclusive access to the block, it broadcasts the essence of the instNction
onto the 604 bus (using the clean operation, described in Table
3-4).
H
the 604 has modilied data associated with the block, the processor
pushes the modified data out of the cache and into the memory queue for
future arbitration onto the 604 bus. In this situation, the cache block is
marked exclusive. Otherwise this instNction is treated as a
no-op.
Data dcbf rA,rB The effective address
Is
computed, translated, and checked for
Cache prdectlon violations as defined by the VEA. H the 604 does not have
Block Rush exclusive access to the
block,
I broadcasts the essence of the instruction
onto the 604 bus (using the flush operation described in Table 3-4). In
addition, if the addressed block is present in the cache, the 604 marks
this data as invaHd. On the dher hand, if the 604 has modified data
associated with the block, the processor pushes the modified data
out
of
the cache and into the memory queue for future aibltratlon onto the 604
bus. In this situation, the
cache
block
Is
marked invalid.
Chapter 2. PowerPC 604 ProceMOr Programming Model 2-51