Instruction Flow; Fetch Unit - IBM PowerPC 604 User Manual

1.2.1 Instruction Flow
Several units on the 604 ensure the proper flow of instructions and operands and guarantee
the correct update of the architectural machine state. These units include the following:
• Fetch unit-Using the next sequential address or the address supplied by the BPU
when a branch is predicted or resolved, the fetch unit supplies instructions to the
eight-word instruction buffer.
• Decode/dispatch unit-The decode/dispatch unit decodes instructions and
dispatches them
to
the appropriate execution unit. During dispatch, operands are
provided
to
the execution unit (or reservation station) from the register files, rename
buffers, and result buses.
• Branch processing unit (BPU)-In addition to providing the fetcher with predicted
target instructions when a branch is predicted (and a mispredict-recovery address if
a branch is incorrectly predicted), the BPU executes all condition register logical
and flow control instructions.
• Completion unit-The completion unit retires executed instructions in program
order and controls the updating of the architectural machine state.
1.2.1.1 Fetch Unit
The fetch unit provides instructions to the eight-entry instruction queue by accessing the
on-chip instruction cache. Typically, the fetch unit continues fetching sequentially as many
as four instructions at a time.
The address of the next instruction to be fetched is determined by several conditions, which
are prioritized as follows:
1·8
1. Detection of an exception. Instruction fetching begins at the exception vector.
2. The BPU recovers from an incorrect prediction when a branch instruction is in the
execute stage. Undispatched instructions are flushed and fetching begins at the
correct target address.
3. The BPU recovers from an incorrect prediction when a branch instruction is in the
dispatch stage. Undispatched instructions are flushed and fetching begins at the
correct target address.
4. The BPU recovers from an incorrect prediction when a branch instruction is in the
decode stage. Subsequent instructions are flushed and fetching begins at the correct
target address.
5. A fetch address is found in the BTAC. As a cache block is fetched, the branch target
address cache (BTAC) and the branch history table (BHT) are searched with the
fetch address. If it is found in the BTAC, the target address from the BTAC is the
first candidate for being the next fetch address.
6. If none of the previous conditions exist, the instruction is fetched from the next
sequential address.
PowerPC 604 RISC Micropr0C8880r User's Manual