IBM PowerPC 604 User Manual page 249

The instruction timing for this example is described cycle-by-cycle as follows:
0. In cycle 0, the first pair of add and fadd instructions is fetched.
1.
In
cycle 1, the second pair of add and fadd instructions is fetched as the first pair is
decoded.
2.
In
cycle 2, the first pair of add and fadd instructions is dispatched, the second pair
is decoded and the br instruction is fetched.
3.
In
cycle 3, the first pair of add and fadd instructions is in execute, the second pair
is in dispatch stage, and the hr instruction is in decode. By this time the target
instruction, add (5) was not found in the instruction cache and arbitration for the line
fill has begun.
4. In cycle 4, the first add instruction completes and writes back, the first fadd
instruction is in the second execute stage, and the second pair of add/fadd
instructions enter execute stage. The br instruction is in dispatch stage and
arbitration continues for the line fill. The target instruction, add (5), and fsub remain
in the fetch state.
5. In cycle 5, fadd (1) is in the final execute stage in the floating-point pipeline, which
prevents the subsequent add instruction from compieting and writing back. The
second fadd instruction is in the second cycle of the floating-point execute stage and
the br instruction is in execute stage. During this cycle, the address for the target
instruction is on the address bus and access has been granted for the data bus.
6. In cycle 6, fadd (1) completes and writes back, allowing the add (2) instruction to
complete and write back. The fadd (3) instruction is in the final execute stage and
the br instruction is in complete stage. The first beat of the four-beat burst (which
contains the critical double word) is sent over the data bus.
7. In cycle 7, fadd (3) completes and writes back, allowing the br instruction to
complete. The second beat of the burst transfer begins on the data bus.
8. In cycle 8, the two instructions in the critical double word transferred in cycles 6 and
7 (add (5) and fsub ( 6)) are placed in the instruction queue. All previous instructions
have vacated the completion buffer.
9. In cycle 9, add (5) and fsub (6) are in decode stage and the pair of instructions
loaded in the second beat of the data burst (add (7) and fsub (8)) are fetched. Note
that although there is room in the instruction queue for as many as four instructions,
only instructions 7 and 8 are available.
10. In
cycle 10, instructions 5 and 6 are in dispatch stage, instructions 7 and 8 are in
decode stage, and the third pair of instructions are fetched The fourth pair of
instructions are sent in the fourth and final beat of the four-beat data burst.
11.
In
the remaining clock cycles, the instructions shown complete processing similarly
to
instructions 0-3. Note again that although the integer instructions add (7) and
add (9) complete, they cannot write back until the previous floating-point
instructions fsub (6) and fsub (8) write back.
Chapter 6. Instruction Timing 6-23