IBM PowerPC 604 User Manual page 228

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6-2
• Superscalar-A superscalar processor is one that can issue multiple instructions
concurrently from a conventional linear instruction stream.
In
a superscalar
implementation, multiple instructions can be in the same stage at the same time. In
the 604 these instructions can leave the execute stage out of order but must leave the
other stages in order.
• Branch prediction-The process of guessing whether a branch will be taken. Such
predictions can be correct or incorrect; the term predicted as it is used here does not
imply that the prediction is correct (successful). The PowerPC architecture defines
a means for static branch prediction, which is part of the instruction encoding. The
604 also implements dynamic branch prediction, where there are levels of
probability assigned to a particular instruction depending on the history of that
instruction, which is recorded in the branch history table (BHT).
• Branch resolution-The determination of whether a branch is taken or not taken. A
branch is said to be resolved when it can exactly be determined which path it will
take.
If
the branch is resolved as predicted, speculatively executed instructions can
be completed.
If
the branch is not resolved as predicted, instructions on the
mispredicted path are purged from the instruction pipeline and are replaced with the
instructions from the nonpredicted path.
• Program order-The original order in which program instructions are provided
to
the instruction queue from the cache.
• Stall-An occurrence when an instruction cannot proceed to
the
next stage.
• Latency-The number of clock cycles necessary to execute an instruction and make
ready the results of that execution for a subsequent instruction.
• Throughput-A measure of the number of instructions that are processed per cycle.
For example, a series of double-precision floating-point multiply instructions has a
throughput of one instruction per clock cycle.
• Reservation station-A buffer between the dispatch and execute stages that allows
instructions
to
be dispatched even though the operands required for execution may
not yet be available.
In
the 604, each execution unit has a two-entry reservation
station.
The
604 implements two types of reservation stations. The integer units
implement out-of-order execution units so integer instructions can be executed out
of order within individual integer units and among the three units. The reservation
stations for the other execution units are in-order reservation stations-that is, all
noninteger instructions must pass through its assigned unit in program order with
respect
to
other like instructions.
PowerPC 604 RISC Microprocessor User's Manual