IBM PowerPC 750GX User Manual

IBM PowerPC 750GX User Manual

Risc microprocessor
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IBM PowerPC 750GX and 750GL RISC Micro-
processor
User's Manual
Version 1.2
March 27, 2006

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Summary of Contents for IBM PowerPC 750GX

  • Page 1 Title Page IBM PowerPC 750GX and 750GL RISC Micro- processor User’s Manual Version 1.2 March 27, 2006...
  • Page 2 The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this docu- ment was obtained in specific environments, and is presented as an illustration.
  • Page 3: Table Of Contents

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor List of Figures ......................13 List of Tables ........................ 15 About This Manual ......................19 Who Should Read This Manual ......................19 Related Publications ..........................19 Conventions Used in This Manual ......................20 Using This Manual with the Programming Environments Manual ............
  • Page 4 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2. Programming Model ....................57 2.1 PowerPC 750GX Processor Register Set ..................57 2.1.1 Register Set ........................... 57 2.1.2 PowerPC 750GX-Specific Registers ..................64 2.1.2.1 Instruction Address Breakpoint Register (IABR) ............64 2.1.2.2 Hardware-Implementation-Dependent Register 0 (HID0) ..........
  • Page 5 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.3.6.1 System Linkage Instructions—OEA ................118 2.3.6.2 Processor Control Instructions—OEA ................118 2.3.6.3 Memory Control Instructions—OEA ................119 2.3.7 Recommended Simplified Mnemonics ................120 3. Instruction-Cache and Data-Cache Operation ............ 121 3.1 Data-Cache Organization ......................
  • Page 6 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 4.2 Exception Recognition and Priorities ..................... 153 4.3 Exception Processing ........................156 4.3.1 Machine Status Save/Restore Register 0 (SRR0) ............... 156 4.3.2 Machine Status Save/Restore Register 1 (SRR1) ............... 157 4.3.3 Machine State Register (MSR) .................... 158 4.3.4 Enabling and Disabling Exceptions ..................
  • Page 7 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 5.1.8 MMU Instructions and Register Summary ................194 5.2 Real-Addressing Mode ........................195 5.3 Block-Address Translation ......................196 5.4 Memory Segment Model ....................... 196 5.4.1 Page History Recording ....................... 196 5.4.1.1 Referenced Bit ......................197 5.4.1.2 Changed Bit ........................
  • Page 8 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 6.6.1.3 Completion-Unit Resource Requirements ..............237 6.7 Instruction Latency Summary ......................238 7. Signal Descriptions ....................249 7.1 Signal Configuration ........................250 7.2 Signal Descriptions ........................251 7.2.1 Address-Bus Arbitration Signals ..................251 7.2.1.1 Bus Request (BR)—Output ..................
  • Page 9 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2.11.4 Time Base Enable (TBEN)—Input ................274 7.2.11.5 TLB Invalidate Synchronize (TLBISYNC)—Input ............274 7.2.12 Processor Mode Selection Signals ..................274 7.2.13 I/O Voltage Select Signals ....................275 7.2.14 Test Interface Signals ......................275 7.2.14.1 IEEE 1149.1a-1993 Interface Description ..............
  • Page 10 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 8.6.2 No-DRTRY Mode ......................... 318 8.7 Processor State Signals ........................ 319 8.7.1 Support for the lwarx and stwcx. Instruction Pair ............... 319 8.7.2 TLBISYNC Input ........................319 8.8 IEEE 1149.1a-1993 Compliant Interface ..................319 8.8.1 JTAG/COP Interface ......................
  • Page 11 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 11.1 Performance-Monitor Interrupt ....................349 11.2 Special-Purpose Registers Used by Performance Monitor ............350 11.2.1 Performance-Monitor Registers ..................351 11.2.1.1 Monitor Mode Control Register 0 (MMCR0) ............... 351 11.2.1.2 User Monitor Mode Control Register 0 (UMMCR0) ............ 351 11.2.1.3 Monitor Mode Control Register 1 (MMCR1) ...............
  • Page 12 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 750gx_umTOC.fm.(1.2) Page 12 of 377 March 27, 2006...
  • Page 13: List Of Figures

    Figure 4-1. SRESET Asserted During HRESET ..................164 Figure 5-1. MMU Conceptual Block Diagram ..................183 Figure 5-2. PowerPC 750GX Microprocessor IMMU Block Diagram ............. 184 Figure 5-3. 750GX Microprocessor DMMU Block Diagram ..............185 Figure 5-4. Address-Translation Types ....................187 Figure 5-5.
  • Page 14 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-5. First Level Address Pipelining ....................287 Figure 8-6. Address-Bus Arbitration ......................290 Figure 8-7. Address-Bus Arbitration Showing Bus Parking ..............291 Figure 8-8. Address-Bus Transfer ......................293 Figure 8-9. Snooped Address Cycle with ARTRY ..................301 Figure 8-10.
  • Page 15: List Of Tables

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor List of Tables Table 1-1. Architecture-Defined Registers (Excluding SPRs) ..............42 Table 1-2. Architecture-Defined SPRs Implemented ................43 Table 1-3. Implementation-Specific Registers ..................44 Table 1-4. 750GX Microprocessor Exception Classifications ..............49 Table 1-5.
  • Page 16 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-34. SPR Encodings for 750GX-Defined Registers (mfspr) ............112 Table 2-35. Memory Synchronization Instructions—UISA ...............113 Table 2-36. Move-from Time Base Instruction ..................114 Table 2-37. Memory Synchronization Instructions—VEA ................115 Table 2-38. User-Level Cache Instructions .....................116 Table 2-39.
  • Page 17 Table 6-8. Floating-Point Instructions ....................242 Table 6-9. Load-and-Store Instructions ....................244 Table 7-1. Transfer Type Encodings for PowerPC 750GX Bus Master ..........256 Table 7-2. PowerPC 750GX Snoop Hit Response ................257 Table 7-3. Data-Transfer Size ....................... 259 Table 7-4.
  • Page 18 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 11-7. HID2 Checkstop Control Bits ....................362 Table 11-8. L2CR Checkstop Control Bits ....................362 List of Tables 750gx_umLOT.fm.(1.2) Page 18 of 377 March 27, 2006...
  • Page 19: About This Manual

    • Shanley, Tom. PowerPC System Architecture, Second Edition. Richardson, TX: Addison-Wesley, 1995. PowerPC Microprocessor Documentation The latest version of this manual, errata, and other IBM documents referred to in this manual can be found at: http://www.ibm.com/chips/techlib. • PowerPC 750GX RISC Microprocessor Datasheet. Provides data about bus timing, signal behavior, elec- trical and thermal characteristics, and other design considerations for each PowerPC implementation.
  • Page 20: Conventions Used In This Manual

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Conventions Used in This Manual Notational Conventions mnemonics Instruction mnemonics are shown in lowercase bold. italics Italics indicate variable command parameters. For example: bcctrx. Book titles in text are set in italics.
  • Page 21 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Terminology Conventions The following table describes terminology conventions used in this manual and the equivalent terminology used in the PowerPC Architecture specification. PowerPC Architecture Specification 750GX User’s Manual Data-storage interrupt (DSI)
  • Page 22: Using This Manual With The Programming Environments Manual

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Using This Manual with the Programming Environments Manual Because the PowerPC Architecture is designed to be flexible to support a broad range of processors, the PowerPC Microprocessor Family: The Programming Environments Manual provides a general description of features that are common to PowerPC processors and indicates those features that are optional or that might be implemented differently in the design of each processor.
  • Page 23: Powerpc 750Gx Overview

    It also describes how the 750GX implementation complies with the PowerPC Architecture definition. Note: In this document, the IBM PowerPC 750GX RISC Microprocessor is abbreviated as 750GX or 750GX RISC Microprocessor.
  • Page 24 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor and data block-address-translation (IBAT and DBAT) arrays, defined by the PowerPC Architecture. During block translation, effective addresses are compared simultaneously with all eight block-address-translation (BAT) entries. For information about the L1 cache, see Chapter 3, Instruction-Cache and Data-Cache Operation, on page 121.
  • Page 25: 750Gx Microprocessor Features

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 1-1. 750GX Microprocessor Block Diagram Instruction Control Unit 128-Bit Additional Features: (4 Instructions) Branch Processing Ifetch • Time Base Cntr/ Unit Decrementer Instruction MMU BTIC • Clock Multiplier • JTAG/COP Interface...
  • Page 26 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor made available from the instruction cache. Typically, if a fetch access hits the BTIC, it provides the first two instructions in the target stream effectively yielding a zero-cycle branch. • 512-entry branch history table (BHT) with two bits per entry for four levels of prediction—not- taken, strongly not-taken, taken, strongly taken.
  • Page 27 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor – Retires as many as two instructions per clock. • Separate on-chip L1 instruction and data caches (Harvard architecture). – 32-KB, 8-way set-associative instruction and data caches. – Pseudo least-recently-used (PLRU) replacement algorithm.
  • Page 28 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor • TLBs are hardware-reloadable (the page table search is performed by hardware). • Bus interface features: – Enhanced 60x bus that pipelines back-to-back reads to a depth of four. A dedicated snoop queue that allows snoop copybacks to also pipeline with up to the four maximum reads.
  • Page 29: Instruction Flow

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 1.2.1 Instruction Flow As shown in Figure 1-1, 750GX Microprocessor Block Diagram, on page 25, the 750GX instruction control unit provides centralized control of instruction flow to the execution units. The instruction unit contains a sequential instruction fetch (Ifetch), 6-entry instruction queue (IQ), dispatch unit, and BPU.
  • Page 30: Completion Unit

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor are flushed from the processor, and instruction fetching resumes along the correct path. The 750GX allows a second branch instruction to be predicted; instructions from the second predicted branch instruction stream can be fetched but cannot be dispatched.
  • Page 31: Independent Execution Units

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor For a more detailed discussion of instruction completion, see Section 6.6.1, Branch, Dispatch, and Comple- tion-Unit Resource Requirements, on page 237. 1.2.2 Independent Execution Units In addition to the BPU, the 750GX has the following five execution units: •...
  • Page 32: Load/Store Unit (Lsu)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 1.2.2.3 Load/Store Unit (LSU) The LSU executes all load-and-store instructions and provides the data-transfer interface between the GPRs, FPRs, and the data-cache/memory subsystem. The LSU functions as a 2-stage pipelined unit, which calcu- lates effective addresses in the first stage.
  • Page 33: On-Chip Level 1 Instruction And Data Caches

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The 750GX supports the following types of memory translation: Real-addressing mode In this mode, translation is disabled (control bit MSR(IR) = 0 for instructions and control bit MSR(DR) = 0 for data). The effective address is used as the physical address to access memory.
  • Page 34: Figure 1-2. L1 Cache Organization

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor written into an 8-word buffer. Subsequent double words are fetched from either the L2 cache or the system memory and written into the buffer. Once the total block is in the buffer, the line is written into the L1 cache in a single cycle.
  • Page 35: On-Chip Level 2 Cache Implementation

    L1 data cache have the next highest priority. The last priority consists of instruction fetch requests from the L1 instruction cache. 1.2.6 System Interface/Bus Interface Unit (BIU) The PowerPC 750GX uses a reduced system signal set, which eliminates some optional 60x bus protocol pins. The system designer needs to make note of these differences. gx_01.fm.(1.2)
  • Page 36 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The address and data buses operate independently. Address and data tenures of a memory access are decoupled to provide more flexible control of bus traffic. The primary activity of the system interface is trans- ferring data and instructions between the processor and system memory.
  • Page 37: Signals

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 1-3. System Interface Address Arbitration Data Arbitration Address Start Data Transfer Address Transfer Data Termination 750GX Transfer Attribute Test and Control Address Termination Clocks Interrupt Processor Status/Control VDD (I/O) The system interface supports address pipelining, which allows the address tenure of one transaction to overlap the data tenure of another.
  • Page 38: Signal Configuration

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Interrupt These signals include the interrupt signal, checkstop signals, and both soft reset and hard reset signals. These signals are used to generate interrupt exceptions and, under various conditions, to reset the processor.
  • Page 39: Figure 1-4. 750Gx Microprocessor Signal Groups

    Signal functionality is described in detail in Chapter 7, Signal Descriptions, on page 249 and Chapter 8, Bus Interface Operation, on page 279. Note: See the PowerPC 750GX Datasheet for a complete list of signal pins. gx_01.fm.(1.2) PowerPC 750GX Overview...
  • Page 40: Clocking

    The 750GX supports various processor-to-bus clock frequency ratios, although not all ratios are available for all frequencies. Configuration of the processor/bus clock ratios is displayed through a 750GX-specific register, HID1. For information about supported clock frequencies, see the PowerPC 750GX Datasheet. 1.3 750GX Microprocessor Implementation The PowerPC Architecture is derived from the Performance Optimized with Enhanced RISC (POWER™)
  • Page 41 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Exception mode Section 1.7, Exception Model, on page 48 describes the exception model of the PowerPC operating environment architecture and the differences in the 750GX exception model. The information in this section is described more fully in Chapter 4, Exceptions, on page 151.
  • Page 42: Powerpc Registers And Programming Model

    Processor State Registers, and sets up all other control mechanisms defined in the PowerPC 750GX processor. While running in user mode (problem state), many of these registers and facilities are not accessible, and any attempt to read or write these register results in a program exception.
  • Page 43: Table 1-2. Architecture-Defined Sprs Implemented

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The OEA defines numerous Special-Purpose Registers that serve a variety of functions, such as providing controls, indicating status, configuring the processor, and performing special operations. During normal execution, a program can access the registers shown in Figure 2-1 on page 58, depending on the program’s access privilege (supervisor or user, determined by the privilege-level (PR) bit in the MSR).
  • Page 44: Table 1-3. Implementation-Specific Registers

    String Word Indexed (lswx) or Store String Word Indexed (stswx) instruction. Table 1-3 describes the SPRs in 750GX that are not defined by the PowerPC Architecture. Section 2.1.2, PowerPC 750GX-Specific Registers, on page 64 gives detailed descriptions of these registers, including bit descriptions.
  • Page 45: Instruction Set

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 1.5 Instruction Set All PowerPC instructions are encoded as single-word (32-bit) instructions. Instruction formats are consistent among all instruction types (the primary operation code is always 6 bits, register operands are always speci- fied in the same bit fields in the instruction), permitting efficient decoding to occur in parallel with operand accesses.
  • Page 46 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor – Translation-lookaside-buffer management instructions These categories do not indicate the execution unit that executes a particular instruction or group of instruc- tions. Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on single-precision (one word) and double-precision (two words) floating-point operands.
  • Page 47: 750Gx Microprocessor Instruction Set

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 1.5.2 750GX Microprocessor Instruction Set 750GX instruction set is defined as follows. • 750GX provides hardware support for all PowerPC instructions. • 750GX implements the following instructions, which are optional in the PowerPC Architecture.
  • Page 48: Exception Model

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 1.7 Exception Model The following sections describe the PowerPC exception model and the 750GX implementation. A detailed description of the 750GX exception model is provided in Chapter 4, Exceptions, on page 151 in this manual.
  • Page 49: 750Gx Microprocessor Exception Implementation

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The PowerPC Architecture supports four types of exceptions: Synchronous, These are caused by instructions. All instruction-caused exceptions are handled precise precisely. That is, the machine state at the time the exception occurs is known and can be completely restored.
  • Page 50: Table 1-5. Exceptions And Conditions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 1-5. Exceptions and Conditions Vector Offset Exception Type Causing Conditions (hex) Reserved 00000 — System reset 00100 Assertion of either HRESET or SRESET or a power-on reset. Assertion of the transfer error acknowledge (TEA) during a data-bus transaction, asser-...
  • Page 51: Memory Management

    BAT arrays are maintained by system software. Instructions and data share the same virtual address model, but could operate in separate segment spaces. The PowerPC 750GX MMU and exception model support demand-paged virtual memory. Virtual memory management permits execution of programs larger than the size of physical memory. Demand-paged implies that individual pages for data and instructions are loaded into physical memory from the system disk only when they are required by an executing program.
  • Page 52: 750Gx Microprocessor Memory-Management Implementation

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 1.8.2 750GX Microprocessor Memory-Management Implementation The 750GX implements separate MMUs for instructions and data. It implements a copy of the Segment Registers in the instruction MMU. However, read and write accesses (Move-from Segment Register [mfsr] and Move-to Segment Register [mtsr]) are handled through the Segment Registers implemented as part of the data MMU.
  • Page 53: Figure 1-5. Pipeline Diagram

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 1-5. Pipeline Diagram Maximum 4-instruction fetch per Fetch clock cycle Maximum 3-instruction dispatch per Dispatch clock cycle (includes one branch instruc- tion) Execute Stage FPU1 FPU2 LSU1 FPU3 LSU2 Maximum 2-instruction completion...
  • Page 54: Power Management

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor • The execution units process instructions from their reservation stations using the operands provided from dispatch, and notifies the completion stage when the instruction has finished execution. With the excep- tion of multiply and divide, integer instructions complete execution in a single cycle.
  • Page 55: Thermal Management

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The nap mode further reduces power consumption by disabling bus snooping, leaving only the Time Base Register and the PLL in a powered state. The 750GX returns to the full-power state upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or a machine-check interrupt (MCP).
  • Page 56: Performance Monitor

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The TAU is controlled through the privileged mtspr and mfspr instructions to the four SPRs provided for configuring and controlling the sensor control logic. The SPRs function as follows. • THRM1 and THRM2 provide the ability to compare the junction temperature against two user-provided thresholds.
  • Page 57: Programming Model

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2. Programming Model This chapter describes the 750GX programming model, emphasizing those features specific to the 750GX processor and summarizing those that are common to PowerPC processors. It consists of three major sections, which describe the following topics.
  • Page 58: Figure 2-1. Powerpc 750Gx Microprocessor Programming Model-Registers

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 2-1. PowerPC 750GX Microprocessor Programming Model—Registers SUPERVISOR MODEL—OEA Configuration Registers USER MODEL—VEA Hardware Processor Machine Implementation Version State Time Base Facility (For Reading) Registers Register Register TBR 268 TBR 269...
  • Page 59 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The PowerPC UISA registers are user-level. General Purpose Registers (GPRs) and Floating Point Registers (FPRs) are accessed through instruction operands. Access to registers can be explicit (by using instructions for that purpose such as mtspr and mfspr instructions) or implicit as part of the execution of an instruction.
  • Page 60: Table 2-1. Additional Msr Bits

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor “PowerPC Register Set” of the PowerPC Microprocessor Family: The Programming Environments Manual. • User-level registers (VEA)—The PowerPC VEA defines the time-base facility (TB), which consists of two 32-bit registers—Time Base Upper (TBU) and Time Base Lower (TBL). The Time Base Registers can be written to only by supervisor-level instructions, but can be read by both user-level and supervisor-level software.
  • Page 61 The BAT registers are implemented in pairs—eight pairs of instruction BATs (IBAT0U–IBAT7U and IBAT0L–IBAT7L) and eight pairs of data BATs (DBAT0U–DBAT7U and DBAT0L–DBAT7L). Figure 2-1, PowerPC 750GX Microprocessor Programming Model— Registers lists the SPR numbers for the BAT registers. For more information, see “BAT Regis- ters”...
  • Page 62: Table 2-2. Additional Srr1 Bits

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Register 1 (SRR1)” in Chapter 2, “PowerPC Register Set” of the PowerPC Microprocessor Fam- ily: The Programming Environments Manual for more information. Note: When a machine-check exception occurs, the 750GX sets one or more error bits in SRR1.
  • Page 63 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor – Hardware-Implementation-Dependent Register 0 (HID0)—This register controls various functions, such as enabling checkstop conditions, and locking, enabling, and invalidating the instruction and data caches, power modes, miss-under-miss, and others. – Hardware-Implementation-Dependent Register 1 (HID1)—This register reflects the state of PLL_CFG[0:4] clock signals, and phase-locked loop (PLL) selection and range bits.
  • Page 64: Powerpc 750Gx-Specific Registers

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.1.2 PowerPC 750GX-Specific Registers This section describes registers that are defined for the 750GX but are not included in the PowerPC Architec- ture. 2.1.2.1 Instruction Address Breakpoint Register (IABR) The Instruction Address Breakpoint Register (IABR) supports the instruction address breakpoint exception.
  • Page 65: Hardware-Implementation-Dependent Register 0 (Hid0)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.1.2.2 Hardware-Implementation-Dependent Register 0 (HID0) The Hardware-Implementation-Dependent Register 0 (HID0) controls the state of several functions within 750GX. HID0 can be accessed with mtspr and mfspr using SPR 1008. Reserved 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...
  • Page 66 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Bits Field Name Description Nap mode enable. Operates in conjunction with MSR[POW]. Nap mode disabled. Nap mode enabled. Doze mode is invoked by setting MSR[POW] while this bit is set. In nap mode, the PLL and the time base remain active.
  • Page 67 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Bits Field Name Description Instruction-cache lock Normal operation. Instruction cache is locked. A locked cache supplies data normally on a hit, but is treated as a cache-inhibited transaction on a miss. On a miss, the transaction to ILOCK the bus or the L2 cache is single-beat.
  • Page 68 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Bits Field Name Description Speculative cache access disable Speculative bus accesses to nonguarded space (G = 0) from both the instruction and data caches are enabled. Speculative bus accesses to nonguarded space in both caches are disabled.
  • Page 69 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Bits Field Name Description Branch history table enable BHT disabled. The 750GX uses static branch prediction as defined by the PowerPC User Instruction Set Architecture (UISA) for those branch instructions the BHT would have otherwise used to predict (that is, those that use the CR as the only mechanism to determine direction).
  • Page 70: Hardware-Implementation-Dependent Register 1 (Hid1)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.1.2.3 Hardware-Implementation-Dependent Register 1 (HID1) The Hardware-Implementation-Dependent Register 1 (HID1) reflects the state of the PLL_CFG[0:4] signals. HID1 can be accessed with mtspr and mfspr using SPR 1009. Reserved 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...
  • Page 71: Hardware-Implementation-Dependent Register 2 (Hid2)

    2.1.2.4 Hardware-Implementation-Dependent Register 2 (HID2) The Hardware-Implementation-Dependent Register 2 (HID2) enables parity. The status bits (25:27) are set when a parity error is detected and cleared by writing '0' to each bit. See the IBM PowerPC 750GX RISC Microprocessor Datasheet for details.
  • Page 72: Performance-Monitor Registers

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.1.2.5 Performance-Monitor Registers This section describes the registers used by the performance monitor, which is described in Chapter 11, Performance Monitor and System Related Features, on page 349. Monitor Mode Control Register 0 (MMCR0) The Monitor Mode Control Register 0 (MMCR0) is a 32-bit SPR provided to specify events to be counted and recorded.
  • Page 73 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Bits Field Name Description Disables counting of PMCn when a performance-monitor interrupt is signaled (that is, ((PMCnINTCONTROL = '1') & (PMCn[0] = '1') & (ENINT = '1')) or when an enabled time- base transition occurs with ((INTONBITTRANS = '1') &...
  • Page 74 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Monitor Mode Control Register 1 (MMCR1) The Monitor Mode Control Register 1 (MMCR1) functions as an event selector for Performance-Monitor Counter Registers 3 and 4 (PMC3 and PMC4). Corresponding events to the MMCR1 bits are described in Performance-Monitor Counter Registers (PMCn).
  • Page 75 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The following tables list the selectable events and their encodings: • Table 11-2, PMC1 Events—MMCR0[19:25] Select Encodings, on page 352. • Table 11-3, PMC2 Events—MMCR0[26:31] Select Encodings, on page 352. • Table 11-4, PMC3 Events—MMCR1[0:4] Select Encodings, on page 353.
  • Page 76 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor User Sampled Instruction Address Register (USIA) The contents of SIA are reflected to USIA, which can be read by user-level software. USIA can be accessed with the mfspr instructions using SPR 939.
  • Page 77: Instruction Cache Throttling Control Register (Ictc)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.1.3 Instruction Cache Throttling Control Register (ICTC) Reducing the rate of instruction fetching can control junction temperature without the complexity and over- head of dynamic clock control. System software can control instruction forwarding by writing a nonzero value to the supervisor-level ICTC register.
  • Page 78: Thermal-Management Registers (Thrmn)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.1.4 Thermal-Management Registers (THRMn) The on-chip thermal-management assist unit provides the following functions: • Compares the junction temperature against user programmed thresholds • Generates a thermal-management interrupt if the temperature crosses the threshold •...
  • Page 79: Thermal-Management Register 3 (Thrm3)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-3. Valid THRM1/THRM2 Bit Settings Description Invalid entry. The threshold in the SPR is not used for comparison. Disable thermal-management interrupt assertion. Set TIN and assert thermal-management interrupt if TIE = 1 and the junction temper- ature exceeds the threshold.
  • Page 80: Thermal-Management Register 4 (Thrm4)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.1.4.3 Thermal-Management Register 4 (THRM4) Due to process and thermal sensor variations, a temperature offset is provided that can be read via an mfspr instruction to THRM4. The TOFFSET field is an 8-bit signed integer that represents the temperature offset measured;...
  • Page 81: L2 Cache Control Register (L2Cr)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.1.5 L2 Cache Control Register (L2CR) The L2 Cache Control Register is a supervisor-level, implementation-specific SPR used to configure and operate the L2 cache. It is cleared by a hard reset or power-on reset.
  • Page 82: Operand Conventions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.2 Operand Conventions This section describes the operand conventions as they are represented in two levels of the PowerPC Archi- tecture—UISA and VEA. Detailed descriptions of conventions used for storing values in registers and memory, accessing PowerPC registers, and representing data in these registers can be found in Chapter 3, “Operand Conventions”...
  • Page 83: Floating-Point Operand And Execution Models-Uisa

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.2.3 Floating-Point Operand and Execution Models—UISA The IEEE 754-1985 standard defines conventions for 64-bit and 32-bit arithmetic. The standard requires that single-precision arithmetic be provided for single-precision operands. The standard permits double-precision arithmetic instructions to have either (or both) single-precision or double-precision operands, but states that single-precision arithmetic instructions should not accept double-precision operands.
  • Page 84: Time-Critical Floating-Point Operation

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.2.3.3 Time-Critical Floating-Point Operation For time-critical applications where deterministic floating-point performance is required, the FPSCR bits must be set with: the non-IEEE mode enabled, the floating-point exception masked, and all sticky bits set to one.
  • Page 85: Table 2-6. Floating-Point Result Data-Type Behavior

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-5. Floating-Point Operand Data-Type Behavior (Page 2 of 2) Operand A Operand B Operand C IEEE Mode Non-IEEE Mode Data Type Data Type Data Type (NI = 0) (NI = 1)
  • Page 86: Instruction Set Summary

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.3 Instruction Set Summary This section describes instructions and addressing modes defined for the 750GX. These instructions are divided into the following functional categories: Integer These include arithmetic and logical instructions. For more information, see Section 2.3.4.1 on page 92.
  • Page 87: Classes Of Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor that the architecture specification refers to simplified mnemonics as extended mnemonics. Programs written to be portable across the various assemblers for the PowerPC Architecture should not assume the existence of mnemonics not described in that document.
  • Page 88: Illegal Instruction Class

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.3.1.3 Illegal Instruction Class Illegal instructions can be grouped into the following categories: • Instructions not defined in the PowerPC Architecture.The following primary opcodes are defined as ille- gal, but might be defined to perform new functions in future extensions to the architecture: 1, 4, 5, 6, 9, 22, 56, 60, 61 •...
  • Page 89: Reserved Instruction Class

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.3.1.4 Reserved Instruction Class Reserved instructions are allocated to specific implementation-dependent purposes not defined by the PowerPC Architecture. Attempting to execute an unimplemented reserved instruction invokes the illegal instruction error handler (a program exception). See Section 4.5.7 on page 170 for information about illegal and invalid instruction exceptions.
  • Page 90: Effective Address Calculation

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.3.2.3 Effective Address Calculation An effective address is the 32-bit sum computed by the processor when executing a memory-access or branch instruction or when fetching the next sequential instruction. For a memory-access instruction, if the...
  • Page 91: Instruction Set Overview

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor For example, if the mtmsr sets the MSR[PR] bit, unless an isync immediately follows the mtmsr instruction, a privileged instruction could be executed or privileged access could be performed without causing an excep- tion even though the MSR[PR] bit indicates user mode.
  • Page 92: Powerpc Uisa Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Summary” in the PowerPC Microprocessor Family: The Programming Environments Manual. These categori- zations are somewhat arbitrary and are provided for the convenience of the programmer and do not neces- sarily reflect the PowerPC Architecture specification.
  • Page 93: Table 2-8. Integer Compare Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-7. Integer Arithmetic Instructions (Page 2 of 2) Name Mnemonic Syntax Add to Zero Extended addze (addze. addzeo addzeo.) rD,rA Subtract from Zero Extended subfze (subfze. subfzeo subfzeo.) rD,rA Negate neg (neg.
  • Page 94: Table 2-9. Integer Logical Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Integer Logical Instructions The logical instructions shown in Table 2-9 on page 94 perform bit-parallel operations on the specified oper- ands. Logical instructions with CR updating enabled (uses dot suffix) and the AND Immediate (andi.) and AND Immediate Shifted (andis.) instructions set the CR[CR0] field to characterize the result of the logical...
  • Page 95: Floating-Point Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The integer rotate instructions are summarized in Table 2-10. For more information, see the PowerPC Micro- processor Family: The Programming Environments Manual. Table 2-10. Integer Rotate Instructions Name Mnemonic Syntax Rotate Left Word Immediate then AND with Mask rlwinm (rlwinm.)
  • Page 96: Table 2-12. Floating-Point Arithmetic Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-12. Floating-Point Arithmetic Instructions Name Mnemonic Syntax Floating Add (Double-Precision) fadd (fadd.) frD,frA,frB Floating Add Single fadds (fadds.) frD,frA,frB Floating Subtract (Double-Precision) fsub (fsub.) frD,frA,frB Floating Subtract Single fsubs (fsubs.)
  • Page 97: Table 2-14. Floating-Point Rounding And Conversion Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Examples of uses of these instructions to perform various conversions can be found in Appendix D, “Floating- Point Models,” in the PowerPC Microprocessor Family: The Programming Environments Manual. Table 2-14. Floating-Point Rounding and Conversion Instructions...
  • Page 98: Load-And-Store Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Note: The PowerPC Architecture states that, in some implementations, the move-to FPSCR fields (mtfsf) instruction might perform more slowly when only some of the fields are updated as opposed to all of the fields.
  • Page 99: Table 2-18. Integer Load Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Little Endian Misaligned Accesses The 750GX supports misaligned single register load-and-store accesses in little-endian mode without causing an alignment exception. However, execution of a load/store multiple or string instruction causes an alignment exception.
  • Page 100 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-18. Integer Load Instructions (Page 2 of 2) Name Mnemonic Syntax Load Byte and Zero with Update Indexed lbzux rD,rA,rB Load Half Word and Zero rD,d(rA) Load Half Word and Zero Indexed...
  • Page 101: Table 2-19. Integer Store Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Integer Store Instructions For integer store instructions, the contents of the source register (rS) are stored into the byte, half word, or word in memory addressed by the EA. Many store instructions have an update form, in which rA is updated with the EA.
  • Page 102: Table 2-20. Integer Load-And-Store With Byte-Reverse Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor If store gathering is enabled and the stores do not fall under the above categories, then an Enforce In-Order Execution of I/O (eieio) or Synchronize (sync) instruction must be used to prevent two stores from being gathered.
  • Page 103: Table 2-22. Integer Load-And-Store String Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Integer Load-and-Store String Instructions The integer load-and-store string instructions allow movement of data from memory to registers, or from registers to memory, without concern for alignment. These instructions can be used for a short move between arbitrary memory locations or to initiate a long move between misaligned memory fields.
  • Page 104: Table 2-23. Floating-Point Load Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor For software compatibility, the other two mode encodings, imprecise-nonrecoverable mode and impre- cise-recoverable mode, default to the precise mode. Note: For the 750GX, the ignore-exceptions mode allows floating-point instructions to complete earlier and, thus, might provide better performance than the precise-exception mode.
  • Page 105: Table 2-24. Floating-Point Store Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-24 summarizes the single-precision and double-precision floating-point store and stfiwx instructions. Table 2-24. Floating-Point Store Instructions Name Mnemonic Syntax Store Floating-Point Single stfs frS,d(rA) Store Floating-Point Single Indexed stfsx frS,rB...
  • Page 106: Branch And Flow-Control Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-26. Store Floating-Point Double Behavior (Page 2 of 2) FPR Precision Data Type Action Single SNaN Store Double Normalized Store Double Denormalized Store Double Zero, infinity, QNaN Store Double SNaN...
  • Page 107: Table 2-27. Branch Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor speculatively executed instructions and restore the machine state to immediately after the branch. This cor- rection can be done immediately upon resolution of the Condition Registers bits. Branch Instructions Table 2-27 lists the branch instructions provided by the PowerPC processors. To simplify assembly language programming, a set of simplified mnemonics and symbols is provided for the most frequently used forms of branch conditional, compare, trap, rotate and shift, and certain other instructions.
  • Page 108: System Linkage Instruction-Uisa

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Trap Instructions The trap instructions shown in Table 2-29 are provided to test for a specified set of conditions. If any of the conditions tested by a trap instruction are met, the system trap type of program exception is taken. For more information, see Section 4.5.7 on page 170.
  • Page 109: Table 2-32. Move-To/Move-From Special-Purpose Register Instructions (Uisa)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Implementation Note: The PowerPC Architecture indicates that in some implementations the Move-to Condition Register Fields (mtcrf) instruction might perform more slowly when only a portion of the fields are updated as opposed to all of the fields. The Condition Register access latency for the 750GX is the same in both cases.
  • Page 110 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-33. PowerPC Encodings (Page 2 of 3) Register Name Access mfspr/mtspr Decimal SPR[5–9] SPR[0–4] DBAT7L 10001 11111 Supervisor (OEA) Both DBAT7U 10001 11110 Supervisor (OEA) Both 00000 10110 Supervisor (OEA)
  • Page 111 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-33. PowerPC Encodings (Page 3 of 3) Register Name Access mfspr/mtspr Decimal SPR[5–9] SPR[0–4] 01000 01100 User (VEA) mfspr 01000 11100 Supervisor (OEA) mtspr 01000 01101 User (VEA) mfspr 01000...
  • Page 112: Table 2-34. Spr Encodings For 750Gx-Defined Registers (Mfspr)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Encodings for the 750GX-specific SPRs are listed in Table 2-34. Table 2-34. SPR Encodings for 750GX-Defined Registers (mfspr) Register Name Access mfspr/mtspr Decimal SPR[5–9] SPR[0–4] DABR 1013 11111 10101 User Both...
  • Page 113: Memory Synchronization Instructions-Uisa

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.3.4.7 Memory Synchronization Instructions—UISA Memory synchronization instructions control the order in which memory operations are completed with respect to asynchronous events, and the order in which memory operations are seen by other processors or memory-access mechanisms.
  • Page 114: Memory Synchronization Instructions-Vea

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-36 shows the mftb instruction. Table 2-36. Move-from Time Base Instruction Name Mnemonic Syntax Move-from Time Base mftb rD, TBR Simplified mnemonics are provided for the mftb instruction so it can be coded with the TBR name as part of the mnemonic rather than requiring it to be coded as an operand.
  • Page 115: Memory Control Instructions-Vea

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-37. Memory Synchronization Instructions—VEA Name Mnemonic Syntax Implementation Notes The eieio instruction is dispatched to the LSU and executes after all previous cache- inhibited or write-through accesses are performed. All subsequent instructions that gen- erate such accesses execute after eieio.
  • Page 116: Table 2-38. User-Level Cache Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-38 summarizes the cache instructions defined by the VEA. Note that these instructions are acces- sible to user-level programs. Table 2-38. User-Level Cache Instructions (Page 1 of 2) Name Mnemonic...
  • Page 117: Optional External Control Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-38. User-Level Cache Instructions (Page 2 of 2) Name Mnemonic Syntax Implementation Notes The EA is computed, translated, and checked for protection violations. • For cache hits with the tag marked exclusive unmodified (E), no further action is taken.
  • Page 118: Powerpc Oea Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor output the 4-bit resource ID (RID) field located in the EAR. The eciwx instruction also loads a word from the data bus that is output by the special device. For more information about the relationship between these instructions and the system interface, see Chapter 7, Signal Descriptions, on page 249.
  • Page 119: Memory Control Instructions-Oea

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2.3.6.3 Memory Control Instructions—OEA Memory control instructions include the following. • Cache-management instructions (supervisor-level and user-level). • Segment register manipulation instructions. • Translation-lookaside-buffer management instructions. This section describes supervisor-level memory control instructions. Section 2.3.5.3, Memory Control Instruc- tions—VEA, on page 115 describes user-level memory control instructions.
  • Page 120: Recommended Simplified Mnemonics

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Translation Lookaside Buffer Management Instructions—(OEA) The address-translation mechanism is defined in terms of the segment descriptors and page table entries (PTEs) PowerPC processors use to locate the logical-to-physical address mapping for a particular access.
  • Page 121: Instruction-Cache And Data-Cache Operation

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 3. Instruction-Cache and Data-Cache Operation The 750GX microprocessor contains separate 32-KB, 8-way set-associative instruction and data caches to allow the execution units and registers rapid access to instructions and data. This chapter describes the orga-...
  • Page 122: Figure 3-1. Cache Integration

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 3-1. Cache Integration Load/Store Unit Instruction Unit (LSU) Instructions (0–127) EA (20–26) Data (0–63) Cache Tags Cache Tags Instruction Cache Data Cache 32-KB PA (0–19) 32-KB 8-Way Set Associative 8-Way Set Associative...
  • Page 123: Data-Cache Organization

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 3.1 Data-Cache Organization The data cache is organized as 128 sets of eight ways as shown in Figure 3-2. Each way consists of 32 bytes, two state bits, and an address tag. Note that in the PowerPC Architecture, the term ‘cache block,’ or simply ‘block,’...
  • Page 124: Instruction-Cache Organization

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 3.2 Instruction-Cache Organization The instruction cache also consists of 128 sets of eight ways, as shown in Figure 3-3 on page 125. Each way consists of 32 bytes, a single state bit, and an address tag. As with the data cache, each instruction-cache block contains eight contiguous words from memory that are loaded from an 8-word boundary (that is, bits A[27–31] of the logical [effective] addresses are zero).
  • Page 125: Memory And Cache Coherency

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 3-3. Instruction-Cache Organization 128 Sets Way 0 Address Tag 0 Valid Words [0–7] Way 1 Address Tag 1 Valid Words [0–7] Way 2 Address Tag 2 Valid Words [0–7] Way 3...
  • Page 126: Mei Protocol

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor These bits allow both uniprocessor and multiprocessor system designs to exploit numerous system-level performance optimizations. The WIMG attributes are programmed by the operating system for each page and block. The write-through (W) and caching-inhibited (I) attributes control how the processor performing an access uses its own cache.
  • Page 127: Table 3-1. Mei State Definitions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 3-1. MEI State Definitions MEI State Definition The addressed cache block is present in the cache, and is modified with respect to system memory. That is, the Modified (M) modified data in the cache block has not been written back to memory. The cache block might be present in 750GX’s L2 cache, but it is not present in any other coherent cache.
  • Page 128: Mei Hardware Considerations

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 3-4. MEI Cache-Coherency Protocol—State Diagram (WIM = 001) Invalid SH/CRW SH/CRW Modified Exclusive SH/CIR Bus Transactions SH = Snoop Hit RH = Read Hit Snoop Push RM = Read Miss...
  • Page 129: Coherency Precautions In Single-Processor Systems

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Another consideration is page table aliasing. If a store hits to a modified cache block but the page table entry is marked write-through (WIMG = 1xxx), then the page has probably been aliased through another page table entry which is marked write-back (WIMG = 0xxx).
  • Page 130: Powerpc 750Gx-Initiated Load/Store Operations

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 3.3.5 PowerPC 750GX-Initiated Load/Store Operations Load-and-store operations are assumed to be weakly ordered on the 750GX. The load/store unit (LSU) can perform load operations that occur later in the program ahead of store operations, even when the data cache is disabled (see Section 3.3.5.2).
  • Page 131: Cache Control

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor atomic access to noncoherent memory. For detailed information on these instructions, see Chapter 2, Pro- gramming Model, on page 57. The lwarx instruction performs a load word from memory operation and creates a reservation for the 32-byte section of memory that contains the accessed word.
  • Page 132: Data-Cache Flash Invalidation

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 3.4.1.1 Data-Cache Flash Invalidation The data cache is automatically invalidated when the 750GX is powered up and during a hard reset. However, a soft reset does not automatically invalidate the data cache. Software must use the HID0 data- cache flash invalidate bit (HID0[DCFI]) if data cache invalidation is desired after a soft reset.
  • Page 133: Instruction-Cache Flash Invalidation

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 3.4.1.4 Instruction-Cache Flash Invalidation The instruction cache is automatically invalidated when the 750GX is powered up and during a hard reset. However, a soft reset does not automatically invalidate the instruction cache. Software must use the HID0 instruction-cache flash invalidate bit (HID0[ICFI]) if instruction-cache invalidation is desired after a soft reset.
  • Page 134: Data Cache Block Touch (Dcbt) And Data Cache Block Touch For Store (Dcbtst)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor are not broadcast, unless broadcast is enabled through the HID0[ABE] configuration bit. Note that dcbi, dcbf, dcbst, and dcbz do broadcast to the 750GX’s L2 cache, regardless of HID0[ABE]. The icbi instruction is never broadcast.
  • Page 135: Data Cache Block Store (Dcbst)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor For this reason, avoid using dcbz for data that is shared in real time and that is not protected during writing through higher-level software synchronization protocols (such as semaphores). Use of dcbz must be avoided for managing semaphores themselves.
  • Page 136: Instruction Cache Block Invalidate (Icbi)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 3.4.2.6 Instruction Cache Block Invalidate (icbi) For the icbi instruction, the effective address is not computed or translated, so it cannot generate a protection violation or exception. This instruction performs a virtual lookup into the instruction cache (index only). All ways of the selected instruction cache set are invalidated.
  • Page 137: Figure 3-5. Plru Replacement Algorithm

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 3-5. PLRU Replacement Algorithm Allocate L0 invalid L0 valid Allocate L1 invalid L1 valid Allocate L2 invalid L2 valid Allocate L3 invalid L3 valid Allocate L4 invalid L4 valid Allocate...
  • Page 138: Cache Flush Operations

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 3-2. PLRU Bit Update Rules Then the PLRU bits are changed to: If the current access is to: 1. x = Does not change If all eight blocks are valid, then a block is selected for replacement according to the PLRU bit encodings shown in Table 3-3.
  • Page 139: Data-Cache Block-Fill Operations

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The data-cache flush assist bit, HID0[DCFA], simplifies the software flushing process. When set, HID0[DCFA] forces the PLRU replacement algorithm to ignore the invalid entries and follow the replacement sequence defined by the PLRU bits. This reduces the series of uniquely addressed load or dcbz instructions to eight per set.
  • Page 140: Read Operations And The Mei Protocol

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Burst transactions on the 750GX always transfer eight words of data at a time, and are aligned to a double- word boundary. The 750GX transfer burst (TBST) output signal indicates to the system whether the current transaction is a single-beat transaction or 4-beat burst transfer.
  • Page 141: Bus Operations Caused By Cache-Control Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 3.6.2 Bus Operations Caused by Cache-Control Instructions The cache-control, TLB management, and synchronization instructions supported by the 750GX can affect or be affected by the operation of the 60x bus. The operation of the instructions can also indirectly cause bus transactions to be performed, or their completion can be linked to the bus.
  • Page 142: Snooping

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 3.6.3 Snooping The 750GX maintains data-cache coherency in hardware by coordinating activity between the data cache, the bus interface logic, the L2 cache, and the memory system. The 750GX has a copy-back cache which relies on bus snooping to maintain cache coherency with other caches in the system.
  • Page 143: Snoop Response To 60X Bus Transactions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor the data transactions to memory in order). Note also that all burst writes by the 750GX are performed as nonglobal, and hence do not normally enable snooping, even for address collision purposes. (Snooping might still occur for reservation cancelling purposes.)
  • Page 144 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 3-5. Response to Snooped Bus Transactions (Page 2 of 3) Snooped Transaction TT[0–4] 750GX Response A write-with-kill operation is a burst transaction initiated due to a castout, caching- enabled push, or snoop copy-back.
  • Page 145: Transfer Attributes

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 3-5. Response to Snooped Bus Transactions (Page 3 of 3) Snooped Transaction TT[0–4] 750GX Response A RWNITC operation is issued to acquire exclusive use of a memory location with no intention of modifying the location.
  • Page 146: Table 3-6. Address/Transfer Attribute Summary

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 3-6. Address/Transfer Attribute Summary Bus Transaction A[0–31] TT[0–4] TBST TSIZ[0–2] Instruction fetch operations: Burst (caching-enabled) PA[0–28] || 0b000 0 1 1 1 0 0 1 0 ¬ M Single-beat read (caching-inhibited or PA[0–28] || 0b000...
  • Page 147: Mei State Transactions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 3.7 MEI State Transactions Table 3-7 shows MEI state transitions for various operations. Bus operations are described in Table 3-4 on page 141. Table 3-7. MEI State Transitions (Page 1 of 3)
  • Page 148 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 3-7. MEI State Transitions (Page 2 of 3) Current Next Cache Operation Cache Cache Cache Actions Bus Operation Operation Sync State State dcbst. — Same Data-cache- dcbst Pass clean. Clean...
  • Page 149 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 3-7. MEI State Transitions (Page 3 of 3) Current Next Cache Operation Cache Cache Cache Actions Bus Operation Operation Sync State State Pass TLBI. — tlbie TLB invalidate No action.
  • Page 150 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Instruction-Cache and Data-Cache Operation gx_03.fm.(1.2) Page 150 of 377 March 27, 2006...
  • Page 151: Exceptions

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor 4. Exceptions The operating environment architecture (OEA) portion of the PowerPC Architecture defines the mechanism by which PowerPC processors implement exceptions (referred to as interrupts in the architecture specifica- tion). Exception conditions can be defined at other levels of the architecture. For example, the user instruction set architecture (UISA) defines conditions that can cause floating-point exceptions;...
  • Page 152: Powerpc 750Gx Microprocessor Exceptions

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor Note: The PowerPC Architecture documentation refers to exceptions as interrupts. In this book, the term “interrupt” is reserved to refer to asynchronous exceptions and sometimes to the event that causes the exception.
  • Page 153: Exception Recognition And Priorities

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor Table 4-2. Exceptions and Conditions (Page 2 of 2) Vector Offset Exception Type Causing Conditions (hex) Program 00700 As defined by the PowerPC Architecture (for example, an instruction opcode error). Floating-point unavail- As defined by the PowerPC Architecture.
  • Page 154 User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor • Exceptions caused by asynchronous events (interrupts). These exceptions are further distinguished by whether they are maskable and recoverable. – Asynchronous, nonmaskable, nonrecoverable System reset for assertion of HRESET—Has highest priority and is taken immediately regardless of other pending exceptions or recoverability (includes power-on reset).
  • Page 155: Table 4-3. Exception Priorities

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor Table 4-3. Exception Priorities Priority Exception Cause Asynchronous Exceptions (Interrupts) System Reset HRESET, POR TEA, 60x address-parity error, 60x data-parity error, L2 ECC double-bit error, MCP, L2-tag Machine Check parity error, data-tag parity error, instruction-tag parity error, instruction-cache parity error,...
  • Page 156: Exception Processing

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor System reset and machine-check exceptions can occur at any time and are not delayed even if an exception is being handled. As a result, state information for an interrupted exception might be lost. Therefore, these exceptions are typically nonrecoverable.
  • Page 157: Machine Status Save/Restore Register 1 (Srr1)

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor 4.3.2 Machine Status Save/Restore Register 1 (SRR1) SRR1 is used to save machine status (selected MSR bits and possibly other status bits as well) on excep- tions and to restore those values when a Return from Interrupt (rfi) instruction is executed.
  • Page 158: Machine State Register (Msr)

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor 4.3.3 Machine State Register (MSR) Reserved ILE EE PR FP ME SE BE IP IR DR PM RI LE 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...
  • Page 159 User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor Bits Field Name Description Branch trace enable The processor executes branch instructions normally. The processor generates a branch-type trace exception when a branch instruc- tion executes successfully. IEEE floating-point exception mode 1 (see Table 4-4 on page 160).
  • Page 160: Enabling And Disabling Exceptions

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor Table 4-4. IEEE Floating-Point Exception Mode Bits Mode Floating-point exceptions disabled. Imprecise nonrecoverable. For this setting, the 750GX operates in floating-point precise mode. Imprecise recoverable. For this setting, the 750GX operates in floating-point precise mode.
  • Page 161: Setting Msr[Ri]

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor 0x000n_nnnn. If IP is set, exceptions are vectored to the physical address 0xFFFn_nnnn. For a machine- check exception that occurs when MSR[ME] = 0 (machine-check exceptions are disabled), the checkstop state is entered (the machine stops executing instructions).
  • Page 162: Process Switching

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor 4.4 Process Switching The following instructions are useful for restoring proper context during process switching: • The Synchronization (sync) instruction orders the effects of instruction execution. All instructions previ- ously initiated appear to have completed before the sync instruction completes, and no subsequent instructions appear to be initiated until the sync instruction completes.
  • Page 163: System Reset Exception (0X00100)

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor Table 4-5. MSR Setting Due to Exception (Page 2 of 2) MSR Bit Exception Type System management — — — Performance monitor — — — Thermal management — — — Note: 1.
  • Page 164: Soft Reset

    SRESET is an effectively edge-sensitive signal that can be asserted and deasserted asynchronously, provided the minimum pulse width specified in the PowerPC 750GX RISC Microprocessor Datasheet is met. Asserting SRESET causes the 750GX to take a system reset exception. This exception modifies the MSR, SRR0, and SRR1, as described in the PowerPC Microprocessor Family: The Programming Environments Manual.
  • Page 165 User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor The hard reset exception is a nonrecoverable, nonmaskable, asynchronous exception. When HRESET is asserted or at power-on reset (POR), the 750GX immediately branches to 0xFFF0_0100 without attempting to reach a recoverable state. A hard reset has the highest priority of any exception. It is always nonrecover- able.
  • Page 166: Table 4-7. Settings Caused By Hard Reset

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor Table 4-7. Settings Caused by Hard Reset Register Setting MMCRn 00000000 Register Setting 00000040 (only IP set) BATs Unknown PMCn Unknown Cache, instruction All blocks are unchanged from before cache, and data See the PowerPC 750GX Datasheet HRESET.
  • Page 167: Machine-Check Exception (0X00200)

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor The following is also true after a hard reset operation: • External checkstops are enabled. • The on-chip test interface has given control of the I/Os to the rest of the chip for functional use.
  • Page 168: Machine-Check Exception Enabled (Msr[Me] = 1)

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor A TEA indication on the bus can result from any load or store operation initiated by the processor. In general, TEA is expected to be used by a memory controller to indicate that a memory parity error or an uncorrectable memory ECC error has occurred.
  • Page 169: Checkstop State (Msr[Me] = 0)

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor When a machine-check exception is taken, instruction fetching resumes at offset 0x00200 from the physical base address indicated by MSR[IP]. 4.5.2.2 Checkstop State (MSR[ME] = 0) If MSR[ME] = 0 and a machine check occurs, the processor enters the checkstop state. The 750GX processor can also be forced into the checkstop state by the assertion of checkstop input (CKSTP_IN), the primary input signal.
  • Page 170: Alignment Exception (0X00600)

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor stops dispatching and waits for all pending instructions to complete. This allows any instructions in progress that need to take an exception to do so before the external interrupt is taken. After all instructions have vacated the completion buffer, the 750GX takes the external interrupt exception as defined in the PowerPC Architecture (OEA).
  • Page 171: Floating-Point Unavailable Exception (0X00800)

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor 4.5.8 Floating-Point Unavailable Exception (0x00800) The floating-point unavailable exception is implemented as defined in the PowerPC Architecture. A floating- point unavailable exception occurs when no higher-priority exception exists, an attempt is made to execute a floating-point instruction (including floating-point load, store, or move instructions), and the floating-point available bit in the MSR is disabled, (MSR[FP] = 0).
  • Page 172: Performance-Monitor Interrupt (0X00F00)

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor 4.5.13 Performance-Monitor Interrupt (0x00F00) The 750GX microprocessor provides a performance-monitor facility to monitor and count predefined events such as processor clocks, misses in either the instruction cache or the data cache, instructions dispatched to a particular execution unit, mispredicted branches, and other occurrences.
  • Page 173: Instruction Address Breakpoint Exception (0X01300)

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor 4.5.14 Instruction Address Breakpoint Exception (0x01300) An instruction address breakpoint interrupt occurs when the following conditions are met: • The instruction breakpoint address IABR[0:29] matches EA[0:29] of the next instruction to complete in program order.
  • Page 174: Thermal-Management Interrupt Exception (0X01700)

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor Table 4-12. System Management Interrupt Exception—Register Settings Register Setting Description Set to the effective address of the instruction that the processor would have attempted to execute next if no exception SRR0 conditions were present.
  • Page 175: Data Address Breakpoint Exception

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor The thermal-management interrupt is similar to the system management and external interrupt. The 750GX requires the next instruction in program order to complete or take an exception, blocks completion of any following instructions, and allows the completed store queue to drain.
  • Page 176: Exception Latencies

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor 4.5.19 Exception Latencies Latencies for taking various exceptions are variable based on the state of the machine when conditions to produce an exception occur. The shortest latency possible is one cycle. In this case, an exception is signaled in the cycle following the appearance of the conditions that generated that exception.
  • Page 177: Timer Facilities

    User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor Table 4-14. Front-End Exception Handling Summary (Page 2 of 2) Exception Type Specific Exception Description Once this type of exception is detected, dispatch is halted and the current instruction stream is allowed to drain out of the machine.
  • Page 178 User’s Manual IBM PowerPC 750GX and GL RISC Microprocessor Exceptions gx_04.fm.(1.2) Page 178 of 377 March 27, 2006...
  • Page 179: Memory Management

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 5. Memory Management This chapter describes the 750GX microprocessor’s implementation of the memory management unit (MMU) specifications provided by the operating environment architecture (OEA) for PowerPC processors. The primary function of the MMU in a PowerPC processor is the translation of logical (effective) addresses to physical addresses (referred to as real addresses in the architecture specification) for memory accesses and I/O accesses (I/O accesses are assumed to be memory-mapped).
  • Page 180: Table 5-1. Mmu Feature Summary

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Basic features of the 750GX MMU implementation defined by the OEA are as follows: • Support for real-addressing mode—Effective-to-physical address translation can be disabled separately for data and instruction accesses. • Block-address translation—Each of the BAT array entries (eight IBAT entries and eight DBAT entries) provides a mechanism for translating blocks as large as 256 MB from the 32-bit effective address space into the physical memory space.
  • Page 181: Memory Addressing

    In the event of a TLB miss, the hardware attempts to load the TLB based on the results of a translation table- search operation. Figure 5-2, PowerPC 750GX Microprocessor IMMU Block Diagram, on page 184 and Figure 5-3, 750GX Microprocessor DMMU Block Diagram, on page 185 show the conceptual organization of the 750GX’s instruction and data MMUs, respectively.
  • Page 182 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor the memory subsystem. The MMUs record whether the translation is for an instruction or data access, whether the processor is in user or supervisor mode, and for data accesses, whether the access is a load or a store operation.
  • Page 183 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 5-1. MMU Conceptual Block Diagram Data Instruction Accesses Accesses EA[0–19] EA[0–19] A[20–31] (32-Bit) EA[4–19] EA[15–19] EA[0–3] EA[0–14] IBAT0U IBAT0L Segment Registers • • • IBAT7U • • IBAT7L EA[15–19] Upper 24-Bits of Virtual Address EA[0–14]...
  • Page 184 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 5-2. PowerPC 750GX Microprocessor IMMU Block Diagram Instruction A[20–31] Unit IMMU EA[0–19] EA[0–3] IBAT Array EA[0–19] Segment Registers IBAT0U IBAT0L Select • EA[0–14] • • • • IBAT7U IBAT7L EA[4–19]...
  • Page 185: Figure 5-3. 750Gx Microprocessor Dmmu Block Diagram

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 5-3. 750GX Microprocessor DMMU Block Diagram A[20–31] Load/Store Unit DMMU EA[0–19] EA[0–3] DBAT Array EA[0–19] Segment Registers DBAT0U DBAT0L Select • EA[0–14] • • • • DBAT7U DBAT7L EA[4–19] DTLB...
  • Page 186: Address-Translation Mechanisms

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 5.1.3 Address-Translation Mechanisms PowerPC processors support the following three types of address translation: Page address Translates the page frame address for a 4-KB page size. Block address Translates the block number for blocks that range in size from 128 KB to 256 MB.
  • Page 187: Memory-Protection Facilities

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 5-4. Address-Translation Types Address Translation Disabled Effective Address (MSR[IR] = 0, or MSR[DR] = 0) Match with BAT Segment Descriptor Registers Located (T = 1) (T = 0) Block Address Translation Page Address (See Section 5.3 on page 196)
  • Page 188: Page History Information

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 5-2. Access Protection Options for Pages User Read Supervisor Read Option User Write Supervisor Write I-Fetch Data I-Fetch Data Supervisor-only Supervisor-only-no-execute Supervisor-write-only Supervisor-write-only-no-execute Both (user/supervisor) Both (user-/supervisor) no-execute Both (user-/supervisor) read-only...
  • Page 189: General Flow Of Mmu Address Translation

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 5.1.6 General Flow of MMU Address Translation The following sections describe the general flow used by PowerPC processors to translate effective addresses to virtual and then physical addresses. 5.1.6.1 Real-Addressing Mode and Block-Address-Translation Selection...
  • Page 190: Page-Address-Translation Selection

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 5.1.6.2 Page-Address-Translation Selection If address translation is enabled and the effective address information does not match a BAT array entry, then the segment descriptor must be located. When the segment descriptor is located, the T bit in the segment descriptor selects whether the translation is to a page or to a direct-store segment as shown in Figure 5-6, General Flow of Page and Direct-Store Interface Address Translation, on page 191.
  • Page 191 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 5-6. General Flow of Page and Direct-Store Interface Address Translation Address Translation with Segment Descriptor Use EA[0–3] to Select One of 16 On-Chip Segment Registers Check T-Bit in Segment Descriptor...
  • Page 192: Mmu Exceptions Summary

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor If the T bit in the Segment Register is cleared (SR[T] = 0), then page-address translation is selected. The information in the segment descriptor is then used to generate the 52-bit virtual address. The virtual address is used to identify the page-address-translation information (stored as page table entries [PTEs] in a page table in memory).
  • Page 193: Table 5-4. Other Mmu Exception Conditions For The 750Gx Processor

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 5-3. Translation Exception Conditions (Page 2 of 2) Condition Description Exception ISI exception Instruction fetch from direct-store seg- Attempt to fetch instruction when SR[T] = 1 ment SRR1[3] =1 DSI exception...
  • Page 194: Mmu Instructions And Register Summary

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 5-4. Other MMU Exception Conditions for the 750GX Processor (Page 2 of 2) Condition Description Exception DSI exception eciwx or ecowx attempted when external eciwx or ecowx attempted with EAR[E] = 0...
  • Page 195: Real-Addressing Mode

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 5-5. 750GX Microprocessor Instruction Summary—Control MMUs (Page 2 of 2) Instruction Description TLB Invalidate Entry ← For effective address specified by rB, TLB[V] The tlbie instruction invalidates all TLB entries indexed by the EA, and operates on both the instruction tlbie rB and data TLBs simultaneously invalidating four TLB entries.
  • Page 196: Block-Address Translation

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor For information on the synchronization requirements for changes to MSR[IR] and MSR[DR], see Section 2.3.2.4, Synchronization, on page 90 in this manual and “Synchronization Requirements for Special Registers and for Lookaside Buffers” in Chapter 2 of the PowerPC Microprocessor Family: The Programming Environments Manual.
  • Page 197: Referenced Bit

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor page-address translation and not for translations made with the BAT mechanism or for accesses that corre- spond to direct-store (T = 1) segments. Furthermore, R and C bits are maintained only for accesses made while address translation is enabled (MSR[IR] = 1 or MSR[DR] = 1).
  • Page 198: Changed Bit

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor • Accesses that cause exceptions and are not completed. 5.4.1.2 Changed Bit The changed bit of a page is located both in the PTE in the page table and in the copy of the PTE loaded into the TLB (if a TLB is implemented, as in the 750GX).
  • Page 199: Page Memory Protection

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 5-8. Model for Guaranteed R and C Bit Settings (Page 2 of 2) Causes Setting of R Bit Causes Setting of C Bit Priority Scenario 750GX 750GX Out-of-order store operation. Required by the sequential...
  • Page 200: Figure 5-7. Segment Register And Dtlb Organization

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Each TLB contains 128 entries organized as a 2-way set-associative array with 64 sets as shown in Figure 5-7 for the DTLB (the ITLB organization is the same). When an address is being translated, a set of two TLB entries is indexed in parallel with the access to a Segment Register.
  • Page 201: Tlb Invalidation

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor To uniquely identify a TLB entry as the required PTE, each TLB entry contains, in addition to the PTE, an additional 4-bit field called the Extended Page Index (EPI). The EPI contains bits 10–13 of the EA. Software cannot access the TLB arrays directly, except to invalidate an entry with the tlbie instruction.
  • Page 202: Page-Address-Translation Summary

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Other than the possible TLB miss on the next instruction prefetch, the tlbie instruction does not affect the instruction fetch operation—that is, the prefetch buffer is not purged and does not cause these instructions to be refetched.
  • Page 203: Figure 5-8. Page-Address-Translation Flow-Tlb Hit

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 5-8. Page-Address-Translation Flow—TLB Hit Effective Address Generated (See Figure 5-6 on page 191) Otherwise Instruction Fetch with N-Bit Set in Segment Descriptor Page Address (No-Execute) Translation Generate 52-Bit Virtual Address...
  • Page 204: Page Table-Search Operation

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 5.4.5 Page Table-Search Operation If the translation is not found in the TLBs (a TLB miss), the 750GX initiates a table-search operation, which is described in this section. Formats for the PTE are given in “PTE Format for 32-Bit Implementations,” in Chapter 7, “Memory Management”...
  • Page 205: Figure 5-9. Primary Page Table Search

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 5-9. Primary Page Table Search Primary Page Table Search Generate PA Using Primary Hash Function PA ← Base PA of PTEG Fetch PTE from PTEG PA ← PA+ 8 Fetch PTE (64-Bits)
  • Page 206: Figure 5-10. Secondary Page-Table-Search Flow

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 5-10. Secondary Page-Table-Search Flow Secondary Page Table Search Generate PA Using Primary Hash Function PA ← Base PA of PTEG Fetch PTE from PTEG PA ← PA+ 8 Fetch PTE (64-Bits)
  • Page 207: Page Table Updates

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 5.4.6 Page Table Updates When TLBs are implemented (as in the 750GX), they are defined as noncoherent caches of the page tables. TLB entries must be flushed explicitly with the TLB invalidate entry instruction (tlbie) whenever the corre- sponding PTE is modified.
  • Page 208 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Memory Management gx_05.fm.(1.2) Page 208 of 377 March 27, 2006...
  • Page 209: Instruction Timing

    IBM PowerPC 750GX and 750GL RISC Microprocessor 6. Instruction Timing This chapter describes how the PowerPC 750GX microprocessor fetches, dispatches, and executes instruc- tions and how it reports the results of instruction execution. It gives detailed descriptions of how the 750GX’s execution units work, and how those units interact with other parts of the processor, such as the instruction- fetching mechanism, register files, and caches.
  • Page 210 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Fetch The process of bringing instructions from the system memory (such as a cache or the main memory) into the instruction queue. Folding (branch folding) On the 750GX, a branch is expunged from (folded out of) the instruction queue via the dispatch mechanism, without being either passed to an execution unit or given a position in the completion queue.
  • Page 211: Instruction Timing Overview

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Stage The processing of instructions in the 750GX is done in stages. They are: fetch, decode/dispatch, execute, complete, and retirement. The fetch unit brings instruc- tions from the memory system into the instruction queue. Once in the instruction queue, the dispatch unit must do a partial decode on the instruction to determine its type.
  • Page 212: Figure 6-1. Pipelined Execution Unit

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor • 64-bit floating-point unit (FPU) • Load/store unit (LSU) • System register unit (SRU) Figure 6-1 represents a generic pipelined execution unit. Figure 6-1. Pipelined Execution Unit Stage 1 Stage 2...
  • Page 213 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The instruction pipeline stages are described as follows: • The instruction fetch stage includes the clock cycles necessary to request instructions from the memory system and the time the memory system takes to respond to the request. Instruction fetch timing depends on many variables, such as whether the instruction is in the branch target instruction cache, the L1 instruction cache, or the L2 cache.
  • Page 214: Figure 6-3. Powerpc 750Gx Microprocessor Pipeline Stages

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The notation conventions used in the instruction timing examples are as follows: Table 6-1. Notation Conventions for Instruction Timing Symbol Description Fetch. The fetch stage includes the time between when an instruction is requested and when it is brought into the instruction queue.
  • Page 215: Timing Considerations

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 6.3 Timing Considerations The 750GX is a superscalar processor; as many as three instructions can be issued to the execution units (one branch instruction to the branch processing unit, and two instructions issued from the dispatch queue to the other execution units) during each clock cycle.
  • Page 216: Instruction Fetch Timing

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The 750GX’s instruction-cache throttling feature, managed through the Instruction Cache Throttling Control (ICTC) register, can lower the processor’s overall junction temperature by slowing the instruction fetch rate. See Chapter 10, Power and Thermal Management, on page 335 for more information.
  • Page 217: Cache Arbitration

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 6.3.2.1 Cache Arbitration When the instruction fetcher requests instructions from the instruction cache, two things might happen. If the instruction cache is idle and the requested instructions are present, they are provided on the next clock cycle.
  • Page 218: Figure 6-4. Instruction Flow Diagram

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 6-4. Instruction Flow Diagram Fetch (Maximum of four instructions per clock cycle) Instruction Queue (In program order) Branch Dispatch (Maximum of two instructions per clock cycle; Processing Unit one instruction per unit)
  • Page 219 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 6-5 on page 220 shows a simple example of instruction fetching that hits in the L1 cache. This example uses a series of integer add and double-precision floating-point add instructions to show how the...
  • Page 220: Figure 6-5. Instruction Timing-Cache Hit

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 6-5. Instruction Timing—Cache Hit ••• Fetch (in IQ) 0 add In dispatch entry (IQ0/IQ1) 1 fadd Execute 2 add Complete (In CQ) 3 fadd In retirement entry (CQ0/CQ1) 5 fsub...
  • Page 221 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The instruction timing for this example is described cycle-by-cycle as follows: 1. In cycle 0, instructions 0–3 are fetched from the instruction cache. Instructions 0 and 1 are placed in the two entries in the instruction queue from which they can be dispatched on the next clock cycle.
  • Page 222: Cache Miss

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 10. In cycle 9, instruction 11 completes, instruction 12 continues through the FPU pipeline, and instructions 13 and 14 are dispatched. One new instruction, 18, can be fetched on this cycle because the instruction queue had one opening on the previous clock cycle.
  • Page 223: Figure 6-6. Instruction Timing-Cache Miss

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 6-6. Instruction Timing—Cache Miss ••• Fetch * 0 add In dispatch entry (IQ0/IQ1) 1 fadd Execute 2 add Complete (In CQ) 3 fadd In retirement entry (CQ0/CQ1) 5 fsub Address...
  • Page 224: L2 Cache Access Timing Considerations

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 6.3.2.4 L2 Cache Access Timing Considerations If an instruction fetch misses both the BTIC and the L1 instruction cache, the 750GX next looks in the L2 cache. If the requested instructions are there, they are burst into the 750GX in much the same way as shown in Figure 6-6 on page 223.
  • Page 225: Instruction Serialization

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor When the dispatch unit dispatches an instruction to its execution unit, it allocates a Rename Register (or registers) for the results of that instruction. If an instruction is dispatched to a reservation station associated with an execution unit due to a data dependency, the dispatcher also provides a tag to the execution unit identifying the Rename Register that forwards the required data at completion.
  • Page 226: Branch Folding

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Performance features such as branch folding, BTIC, dynamic branch prediction (implemented in the BHT), 2-level branch prediction, and the implementation of nonblocking caches minimize the penalties associated with flow-control operations on the 750GX. The timing for branch instruction execution is determined by many factors including: •...
  • Page 227: Branch Instructions And Completion

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 6-7. Branch Taken Branch Folding Branch Folding (Taken Branch/BTIC Hit) (Taken Branch/BTIC Miss) Clock 0 Clock 1 Clock 2 Clock 0 Clock 1 Clock 2 add5 add5 add4 add4 add3...
  • Page 228: Branch Prediction And Resolution

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 6-9. Branch Completion Branch Completion (LR/CTR Write-Back) Clock 0 Clock 1 Clock 2 Clock 3 add5 add4 add3 add5 add7 add9 add4 add6 add8 add2 add3 add5 add7 add1 add4...
  • Page 229 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor does not write back its results to the architected registers. Instead, it stalls in the completion queue. Of course, when the completion queue is full, no additional instructions can be dispatched, even if an execution unit is idle.
  • Page 230 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Predicted Branch Timing Examples Figure 6-10 on page 231 shows cases where branch instructions are predicted. It shows how both taken and not-taken branches are handled, and how the 750GX handles both correct and incorrect predictions. The...
  • Page 231: Figure 6-10. Branch Instruction Timing

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 6-10. Branch Instruction Timing ••• 0 add Fetch 1 add In dispatch entry (IQ0/IQ1) 2 bc Predict 3 mulhw Execute 4 bc Complete (In CQ) 5 fadd In retirement entry (CQ0/CQ1)
  • Page 232: Integer Unit Execution Timing

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 2. In clock cycle 1, instructions 2 and 3 enter the dispatch entries in the IQ. Instruction 4 (a second bc instruction) and 5 are fetched. The second bc instruction is predicted as taken. It can be folded, but it cannot be resolved until instruction 3 writes back.
  • Page 233: Load/Store Unit Execution Timing

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 6.4.5 Load/Store Unit Execution Timing The execution of most load-and-store instructions is pipelined. The LSU has two pipeline stages. The first is for effective address calculation and MMU translation, and the second is for accessing data in the cache.
  • Page 234: Integer Store Gathering

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 6-2. Performance Effects of Memory Operand Placement (Page 2 of 2) Operand Boundary Crossing Protection Size Byte Alignment None 8 Byte Cache Block Boundary Floating-Point Optimal — — — 8 byte —...
  • Page 235: Memory Performance Considerations

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 6.5 Memory Performance Considerations Because the 750GX can have a maximum instruction throughput of three instructions per clock cycle, lack of memory bandwidth can affect performance. For the 750GX to maximize performance, it must be able to read and write data efficiently.
  • Page 236: Effect Of Tlb Miss

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 6.5.2 Effect of TLB Miss If a page-address translation is not in a translation lookaside buffer (TLB), the 750GX hardware searches the page tables and updates the TLB when a translation is found. Table 6-3 shows the estimated latency for the hardware TLB load for different cache configurations and conditions.
  • Page 237: Branch, Dispatch, And Completion-Unit Resource Requirements

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 6.6.1 Branch, Dispatch, and Completion-Unit Resource Requirements This section describes the specific resources required to avoid stalls during branch resolution, instruction dispatching, and instruction completion. 6.6.1.1 Branch-Resolution Resource Requirements The following branch instructions and resources are required to avoid stalling the fetch unit in the course of branch resolution: •...
  • Page 238: Instruction Latency Summary

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor • Requirements for completing an instruction from CQ1: – Instruction in CQ0 must complete in same cycle. – Instruction in CQ1 must be finished. – Instruction in CQ1 must not follow an unresolved predicted branch.
  • Page 239 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 6-5. System-Register Instructions (Page 2 of 2) Primary Extended Instruction Mnemonic Unit Cycles Serialization Opcode Opcode mfspr (data block-address Execution translations [DBATs]) mfspr Move-from Special (instruction Purpose Register block-address —...
  • Page 240: Table 6-6. Condition Register Logical Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 6-6 lists condition register logical instruction latencies. Table 6-6. Condition Register Logical Instructions Primary Extended Instruction Mnemonic Unit Cycles Serialization Opcode Opcode Condition Register AND crand Execution Condition Register AND...
  • Page 241 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 6-7. Integer Instructions (Page 2 of 3) Primary Extended Instruction Mnemonic Unit Cycles Serialization Opcode Opcode AND Immediate Shifted andis. — IU1/IU2 — and[.] IU1/IU2 — Compare IU1/IU2 — Compare Immediate cmpi —...
  • Page 242: Table 6-8. Floating-Point Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 6-7. Integer Instructions (Page 3 of 3) Primary Extended Instruction Mnemonic Unit Cycles Serialization Opcode Opcode Subtract From Carrying subfc[o][.] IU1/IU2 — Subtract From subfe[o][.] IU1/IU2 Execution Extended Subtract From subfic —...
  • Page 243 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 6-8. Floating-Point Instructions (Page 2 of 2) Primary Extended Instruction Mnemonic Unit Cycles Serialization Opcode Opcode Floating Multiply- fmsubs[.] 1-1-1 — Subtract Single Floating Multiply- fmsub[.] 2-1-1 — Subtract Floating Multiply Single fmuls[.]...
  • Page 244: Table 6-9. Load-And-Store Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 6-9 shows load-and-store instruction latencies. Pipelined load/store instructions are shown with cycles of total latency and throughput cycles separated by a colon. Table 6-9. Load-and-Store Instructions (Page 1 of 4)
  • Page 245 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 6-9. Load-and-Store Instructions (Page 2 of 4) Primary Extended Instruction Mnemonic Unit Cycles Serialization Opcode Opcode Load Floating-Point lfsx — Single Indexed Load Halfword — — Algebraic Load Halfword lhau —...
  • Page 246 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 6-9. Load-and-Store Instructions (Page 3 of 4) Primary Extended Instruction Mnemonic Unit Cycles Serialization Opcode Opcode Store Floating-Point stfd — — Double Store Floating-Point stfdu — — Double with Update...
  • Page 247 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 6-9. Load-and-Store Instructions (Page 4 of 4) Primary Extended Instruction Mnemonic Unit Cycles Serialization Opcode Opcode Store Word with Update stwux — Indexed Store Word Indexed stwx — TLB Invalidate Entry...
  • Page 248 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Instruction Timing gx_06.fm.(1.2) Page 248 of 377 March 27, 2006...
  • Page 249: Signal Descriptions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7. Signal Descriptions This chapter describes the 750GX microprocessor’s external signals. It contains a concise description of indi- vidual signals, showing behavior when the signal is asserted and negated and when the signal is an input and an output.
  • Page 250: Signal Configuration

    IBM PowerPC 750GX and 750GL RISC Microprocessor 7.1 Signal Configuration Figure 7-1 illustrates the 750GX’s signal configuration, showing how the signals are grouped. A pinout showing pin numbers is included in the PowerPC 750GX RISC Microprocessor Datasheet. Figure 7-1. 750GX Signal Groups ADDRESS...
  • Page 251: Signal Descriptions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2 Signal Descriptions This section summarizes the functions of individual signals on the 750GX, grouped according to Figure 7-1. Chapter 8, Bus Interface Operation, on page 279 describes many of these signals in greater detail, both with respect to how individual signals function and to how the groups of signals interact.
  • Page 252: Bus Grant (Bg)-Input

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2.1.2 Bus Grant (BG)—Input State Asserted Indicates that the 750GX may, with proper qualification, assume mastership of the address bus. A qualified bus grant occurs when BG is asserted and ABB and ARTRY are not asserted on the bus cycled following the assertion of AACK.
  • Page 253: Address Transfer Start Signals

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Address Bus Busy (ABB)—Input State Asserted Indicates that another master is the current address-bus owner. Negated Indicates that the address bus might be available for use by the 750GX (see BG).
  • Page 254: Address Transfer Signals

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2.3 Address Transfer Signals The address transfer signals are used to transmit the address and to generate and monitor parity for the address transfer. For a detailed description of how these signals interact, see Section 8.3.2, Address Transfer, on page 292.
  • Page 255: Address-Bus Parity (Ap[0-3])

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2.3.2 Address-Bus Parity (AP[0–3]) The address-bus parity (AP[0–3]) signals are both input and output signals reflecting 1 bit of odd-byte parity for each of the 4 bytes of address when a valid address is on the bus.
  • Page 256: Transfer Type (Tt[0-4])

    Timing Assertion/ The same as A[0–31]. Negation Table 7-1 describes the transfer encodings for the 750GX bus master. Table 7-1. Transfer Type Encodings for PowerPC 750GX Bus Master (Page 1 of 2) 750GX Bus 60x Bus Specification Transaction Source Transaction...
  • Page 257: Table 7-2. Powerpc 750Gx Snoop Hit Response

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 7-1. Transfer Type Encodings for PowerPC 750GX Bus Master (Page 2 of 2) 750GX Bus 60x Bus Specification Transaction Source Transaction Master Transaction Command Load Word And Reserve Indexed (lwarx)
  • Page 258: Transfer Size (Tsiz[0-2])-Output

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 7-2. PowerPC 750GX Snoop Hit Response (Page 2 of 2) PowerPC 750GX Bus 60x Bus Specification Command Transaction Snooper; Action on Hit eieio Address only External control word write Single-beat write...
  • Page 259: Transfer Burst (Tbst)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Timing Assertion/ The same as A[0–31]. Negation/ High Impedance Table 7-3. Data-Transfer Size TBST TSIZ[0–2] Transfer Size Asserted Burst (32 bytes) Negated 8 bytes Negated 1 byte Negated 2 bytes Negated...
  • Page 260: Cache Inhibit (Ci)-Output

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2.4.4 Cache Inhibit (CI)—Output The cache inhibit (CI) signal is an output signal on the 750GX. State Asserted Indicates that a single-beat transfer will not be cached, reflecting the setting of the I bit for the block or page that contains the address of the current transaction.
  • Page 261: Global (Gbl)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2.4.6 Global (GBL) The global (GBL) signal is an input/output signal on the 750GX. Global (GBL)—Output State Asserted Indicates that the transaction is global and should be snooped by other masters. GBL reflects the M bit (WIMG bits) from the memory management unit (MMU) except during certain transactions.
  • Page 262: Address Transfer Termination Signals

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2.5 Address Transfer Termination Signals The address transfer termination signals are used to indicate either that the address phase of the transaction has completed successfully or must be repeated, and when it should be terminated. For detailed information about how these signals interact, see Chapter 8, Bus Interface Operation, on page 279.
  • Page 263: Address Retry (Artry)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2.5.2 Address Retry (ARTRY) The address retry (ARTRY) signal is both an input and output signal on the 750GX. Address Retry (ARTRY)—Output State Asserted The 750GX as snooper indicates that the 750GX requires the snooped trans- action to be rerun.
  • Page 264: Data-Bus Arbitration Signals

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Address Retry (ARTRY)—Input State Asserted If the 750GX is the address-bus master, ARTRY indicates that the 750GX must retry the preceding address tenure and immediately negate BR (if asserted). If the associated data tenure has already started, the 750GX also cancels the data tenure immediately, even if the burst data has been received.
  • Page 265: Data-Bus Write-Only (Dbwo)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Negated Indicates that the 750GX is not granted next data-bus ownership. Timing Assertion Might occur on any cycle; not recognized until the cycle TS is asserted, or later. Negation Might occur on any cycle to indicate the 750GX cannot assume data-bus ownership.
  • Page 266: Data-Transfer Signals

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Timing Assertion Occurs the cycle following a qualified DBG. Remains asserted for the dura- tion of the data tenure. Negation Negates for a fraction of a bus cycle (one-half minimum, depends on clock...
  • Page 267: Data-Bus Parity (Dp[0-7])

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Data Bus (DH[0–31], DL[0–31])—Output State Asserted/ Represents the state of data during a data write. For single-beat (cache Negated inhibited or write through) writes, byte lanes not selected for data transfer will not supply valid data (no data mirroring).
  • Page 268: Data Bus Disable (Dbdis)-Input

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Data-Bus Parity (DP[0–7])—Input State Asserted/ Represents odd parity for each byte of read data. Parity is checked on all Negated data byte lanes, regardless of the size of the transfer. Detected even parity causes a checkstop if data-parity errors are enabled in the HID0 register.
  • Page 269: Data Retry (Drtry)-Input

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Timing Assertion Might occur on any cycle during the normal or extended data-bus tenure for the 750GX (see DBB and DRTRY). Must not occur two cycles or more before ARTRY assertion if ARTRY cancellation is to be used.
  • Page 270: System Status Signals

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Timing Assertion/ Assertion might occur on any cycle during the normal or extended data-bus Negation tenure for the 750GX (during DBB, and the cycle after TA during reads). Assertion should occur for one cycle only.
  • Page 271: Machine-Check Interrupt (Mcp)-Input

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2.9.3 Machine-Check Interrupt (MCP)—Input State Asserted The 750GX initiates a machine-check interrupt operation if MSR[ME] and HID0[EMCP] are set. If MSR[ME] is cleared and HID0[EMCP] is set, the 750GX must terminate operation by internally gating off all clocks, and releasing all outputs (except CKSTP_OUT) to the high-impedance state.
  • Page 272: Reset Signals

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2.10 Reset Signals There are two reset signals on the 750GX—hard reset (HRESET) and soft reset (SRESET). Descriptions of the reset signals follows. 7.2.10.1 Hard Reset (HRESET)—Input The hard reset (HRESET) signal must be used at power-on in conjunction with the test reset (TRST) signal to properly reset the processor.
  • Page 273: Processor Status Signals

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2.11 Processor Status Signals Processor status signals indicate the state of the processor. They include the memory reservation signal, machine quiesce control signals, time-base enable signal, and TLB Invalidate Synchronize (TLBISYNC) signal.
  • Page 274: Time Base Enable (Tben)-Input

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2.11.4 Time Base Enable (TBEN)—Input State Asserted Indicates that the time base and decrementer should continue clocking. This signal is essentially a “count enable” control for the time base and decre- menter counter.
  • Page 275: I/O Voltage Select Signals

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 7.2.13 I/O Voltage Select Signals Table 7-7 shows the settings for the I/O voltage signals. Table 7-7. Bus Voltage Selection Settings Select #2 Select #1 Voltage Selection BVSEL L1TSTCLK Reserved 1.8 V 2.5 V...
  • Page 276: L1_Tstclk

    The PLL is configured by the PLL_CFG(0:4) pins. These pins select the multiplier that the PLL will use to multiply the SYSCLK frequency up to the internal core frequency. In addition, the pins PLL_RNG(0:1) must be set to select the appropriate frequency operating range of the PLL. See the PowerPC 750GX Datasheet for more information.
  • Page 277: System Clock (Sysclk)-Input

    7.2.15.3 PLL Configuration (PLL_CFG[0:4])—Input The PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency, the PLL configu- ration signals set the internal CPU frequency of operation. See the PowerPC 750GX Datasheet for PLL configuration. State...
  • Page 278: Pll Range (Pll_Rng[0:1])-Input

    See the PowerPC 750GX Datasheet for information on how to use this signal. • GND and OGND—The GND and OGND signals provide the connection for grounding the 750GX. On the 750GX, there is no electrical distinction between the GND and OGND signals.
  • Page 279: Bus Interface Operation

    IBM PowerPC 750GX and 750GL RISC Microprocessor 8. Bus Interface Operation This chapter describes the PowerPC 750GX microprocessor’s bus interface and its operation. It shows how the 750GX signals, defined in Chapter 7, Signal Descriptions, on page 249, interact to perform address and data transfers.
  • Page 280: Bus Interface Overview

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-1. Bus Interface Address Buffers Instruction Cache Data Cache Interface Instruction Data Cache Data Cache Reservation Data Cache Unit Cache Castout/ Snoop Address Load Castout (BIU) Load Store Address Buffer...
  • Page 281: Operation Of The Instruction And Data L1 Caches

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor In addition to the loads, stores, and instruction fetches, the 750GX performs hardware table-search opera- tions following translation lookaside buffer (TLB) misses, L2 cache castout operations when the least-recently used (LRU) cache lines are written to memory after a cache miss, and cache-line snoop push-out operations when a modified cache line experiences a snoop hit from another bus master.
  • Page 282: Operation Of The Bus Interface

    Figure 8-2 on page 283 is a legend of the conventions used in the timing diagrams. This is a synchronous interface—all 750GX input signals are sampled and output signals are driven on the rising edge of the bus clock cycle (see the PowerPC 750GX Datasheet for exact timing information). 8.1.3 Bus Signal Clocking...
  • Page 283: Direct-Store Accesses

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor one, two, or eight beats depending on the size of the program transaction and the cache mode for the address. For additional information about 32-bit data bus mode, see Section 8.6.1, 32-Bit Data Bus Mode, on page 316.”...
  • Page 284: Memory-Access Protocol

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 8.2 Memory-Access Protocol Memory accesses are divided into address and data tenures. Each tenure has three phases—bus arbitration, transfer, and termination. The 750GX also supports address-only transactions. Note that address and data tenures can overlap, as shown in Figure 8-3.
  • Page 285: Arbitration Signals

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Data tenure: Arbitration To begin the data tenure, the 750GX arbitrates for mastership of the data bus. Transfer After the 750GX is the data-bus master, it samples the data bus for read operations or drives the data bus for write operations.
  • Page 286: Miss-Under-Miss

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor DBWO (data-bus write- Assertion indicates that the 750GX might perform the data-bus tenure for an only) outstanding write address even if a read address is pipelined before the write address. If DBWO is asserted, the 750GX will assume data-bus mastership for a pending data-bus write operation.
  • Page 287: Miss-Under-Miss And System Performance

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor data cache. If there is a miss in the L2 cache, then the request is passed on to the bus interface unit (BIU) via three additional L2-to-BIU reload-request queues. Data returned from the bus is loaded into the data-cache reload buffer, one of the L2 reload buffers, and the critical word is forwarded to the load/store unit.
  • Page 288 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The BIU has both AR buffers and a 4-deep reload-request queue. So, the BIU operation for the MuM support is not dependent on the LSU queue, as it has enough buffers and queue depth to manage the outstanding transactions.
  • Page 289 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Load multiple and load string instructions allow one MuM (two outstanding miss requests) to pipeline on the 60x bus. 6. A load is aliased to a store in the store queue, which means it references a byte to the same index and word.
  • Page 290: Speculative Loads And Conditional Branches

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 8.2.2.2 Speculative Loads and Conditional Branches Loads that are dispatched before a preceding conditional branch is resolved are speculative. Mispredicted branches cause the speculative loads to be canceled. Normally, the cancellation is confined to the load/store unit, and no additional cycles are wasted.
  • Page 291: Figure 8-7. Address-Bus Arbitration Showing Bus Parking

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor External arbiters must allow only one device at a time to be the address-bus master. For implementations in which no other device can be a master, BG can be grounded (always asserted) to continually grant master- ship of the address bus to the 750GX.
  • Page 292: Address Transfer

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor System designers should note that it is possible to ignore the ABB signal, and regenerate the state of ABB locally within each device by monitoring the TS and AACK input signals. The 750GX allows this operation by using both the ABB input signal and a locally regenerated version of ABB to determine if a qualified bus grant state exists (both sources are internally ORed together).
  • Page 293: Figure 8-8. Address-Bus Transfer

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-8. Address-Bus Transfer qual BG ADDR+ aack artry_in gx_08.fm.(1.2) Bus Interface Operation March 27, 2006 Page 293 of 377...
  • Page 294: Address-Bus Parity

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 8.3.2.1 Address-Bus Parity The 750GX always generates 1 bit of correct odd-byte parity for each of the 4 bytes of address when a valid address is on the bus. The calculated values are placed on the AP[0–3] outputs when the 750GX is the address-bus master.
  • Page 295: Burst Ordering During Data Transfers

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The basic coherency size of the bus is defined to be 32 bytes (corresponding to one cache line). Data trans- fers that cross an aligned, 32-byte boundary either must present a new address onto the bus at that boundary (for coherency consideration) or must operate as noncoherent data with respect to the 750GX.
  • Page 296: Effect Of Alignment In Data Transfers

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 8-3. Burst Ordering—32-Bit Bus For Starting Address: Data Transfer A[27–28] = 00 A[27–28] = 01 A[27–28] = 10 A[27–28] = 11 First data beat DW0-U DW1-U DW2-U DW3-U Second data beat...
  • Page 297 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 8-4. Aligned Data Transfers (Page 2 of 2) Data-Bus Byte Lane(s) Transfer Size TSIZ0 TSIZ1 TSIZ2 A[29–31] — — — — Word — — — — Double word Note: The entries with an “x” indicate the byte portions of the requested operand that are read or written during a bus transaction.
  • Page 298: Table 8-5. Misaligned Data Transfers (4-Byte Examples)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 8-5. Misaligned Data Transfers (4-Byte Examples) Data-Bus Byte Lanes Transfer Size TSIZ[0–2] A[29–31] (Four Bytes) Aligned 1 0 0 0 0 0 — — — — Misaligned—first access 0 1 1 0 0 1 —...
  • Page 299: Table 8-7. Misaligned 32-Bit Data-Bus Transfer (4-Byte Examples)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 8-6. Aligned Data Transfers (32-Bit Bus Mode) (Page 2 of 2) Data-Bus Byte Lanes Transfer Size TSIZ0 TSIZ1 TSIZ2 A[29–31] — — — — Half word — — — —...
  • Page 300: Alignment Of External Control Instructions

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 8.3.2.5 Alignment of External Control Instructions The size of the data transfer associated with the eciwx and ecowx instructions is always 4 bytes. If the eciwx or ecowx instruction is misaligned and crosses any word boundary, the 750GX will generate an alignment exception.
  • Page 301: Data-Bus Tenure

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor address tenures occur until the current snoop push from the 750GX is completed. Snoop push delays can also be avoided by operating the L2 cache in write-through mode so no snoop pushes are required by the L2 cache.
  • Page 302: Using The Dbb Signal

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-10. Data-Bus Arbitration drtry qual DBG A qualified data-bus grant can be expressed as the following: QDBG = DBG asserted while DBB, DRTRY, and ARTRY (associated with the data-bus operation) are negated.
  • Page 303: Data-Bus Write-Only

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 8.4.2 Data-Bus Write-Only As a result of address pipelining, the 750GX can have up to two data tenures queued to perform when it receives a qualified DBG. Generally, the data tenures should be performed in strict order (the same order as their address tenures were performed).
  • Page 304: Normal Single-Beat Termination

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor (or only) data beat, the 750GX negates DBB but still considers the data beat active and waits for another assertion of TA. DRTRY is ignored on write operations. TEA indicates a nonrecoverable bus error event.
  • Page 305: Figure 8-12. Normal Single-Beat Write Termination

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-12. Normal Single-Beat Write Termination qual DBG data drtry AACK Normal termination of a burst transfer occurs when TA is asserted for four bus clock cycles, as shown in Figure 8-13. The bus clock cycles in which TA is asserted need not be consecutive, thus allowing pacing of the data-transfer beats.
  • Page 306: Figure 8-14. Termination With Drtry

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor For read bursts, DRTRY can be asserted one bus clock cycle after TA is asserted to signal that the data presented with TA is invalid and that the processor must wait for the negation of DRTRY before forwarding data to the processor (see Figure 8-14).
  • Page 307: Data-Transfer Termination Due To A Bus Error

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-15 shows the effect of using DRTRY during a burst read. It also shows the effect of using TA to pace the data-transfer rate. Notice that in bus clock cycle 3 of Figure 8-15, TA is negated for the second data beat.
  • Page 308: Memory Coherency-Mei Protocol

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Note: TEA generates a machine-check exception depending on MSR[ME]. Clearing the machine-check- exception enable control bits leads to a true checkstop condition (instruction execution halted and processor clock stopped). 8.4.5 Memory Coherency—MEI Protocol The 750GX provides dedicated hardware to provide memory coherency by snooping bus transactions.
  • Page 309: Timing Examples

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-16. MEI Cache-Coherency Protocol—State Diagram (WIM = 001) Invalid SH/CRW SH/CRW Modified Exclusive SH/CIR Bus Transactions SH = Snoop Hit RH = Read Hit Snoop Push RM = Read Miss...
  • Page 310: Figure 8-17. Fastest Single-Beat Reads

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-17. Fastest Single-Beat Reads A[0–31] CPU A CPU A CPU A TT[0–4] Read Read Read TBST AACK ARTRY D[0–63] DRTRY Bus Interface Operation gx_08.fm.(1.2) Page 310 of 377 March 27, 2006...
  • Page 311: Figure 8-18. Fastest Single-Beat Writes

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-18 illustrates the fastest single-beat writes supported by the 750GX. All bidirectional signals are tristated between bus tenures. Figure 8-18. Fastest Single-Beat Writes A[0–31] CPU A CPU A CPU A TT[0–4]...
  • Page 312: Figure 8-19. Single-Beat Reads Showing Data-Delay Controls

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-19 shows three ways to delay single-beat reads using data-delay controls: • The TA signal can remain negated to insert wait states in clock cycles 3 and 4. • For the second access, DBG could have been asserted in clock cycle 6.
  • Page 313: Figure 8-20. Single-Beat Writes Showing Data-Delay Controls

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-20 shows data-delay controls in a single-beat write operation. Note that all bidirectional signals are tristated between bus tenures. Data transfers are delayed in the following ways: • The TA signal is held negated to insert wait states in clocks 3 and 4.
  • Page 314: Figure 8-21. Burst Transfers With Data-Delay Controls

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-21 shows the use of data-delay controls with burst transfers. Note that all bidirectional signals are tristated between bus tenures. Also note: • The first data beat of burst read data (clock 0) is the critical quadword.
  • Page 315: Figure 8-22. Use Of Transfer Error Acknowledge (Tea)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-22 shows the use of the TEA signal. Note that all bidirectional signals are tristated between bus tenures. Also note: • The first data beat of the read burst (in clock 0) is the critical quadword.
  • Page 316: Optional Bus Configuration

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 8.6 Optional Bus Configuration The 750GX supports optional bus configurations that are selected during the negation of the HRESET signal. The operation and selection of the optional bus configuration are described in the following sections.
  • Page 317: Figure 8-23. 32-Bit Data-Bus Transfer (8-Beat Burst)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-23. 32-Bit Data-Bus Transfer (8-Beat Burst) ADDR TBST AACK ARTRY DH[0–31] DRTRY An example of a two-beat data transfer (with DRTRY asserted during each data tenure) is shown in Figure 8-24.
  • Page 318: No-Drtry Mode

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 750GX selects 64-bit or 32-bit data bus mode at startup by sampling the state of the TLBISYNC signal at the negation of HRESET. If the TLBISYNC signal is negated at the negation of HRESET, the 750GX enters 64-bit data mode.
  • Page 319: Processor State Signals

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 8.7 Processor State Signals This section describes the 750GX's support for atomic update and memory through the use of the lwarx and stwcx. opcode pair, and includes a description of the TLB Invalidate Synchronize (TLBISYNC) input.
  • Page 320: Using Data-Bus Write-Only

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 8-25. IEEE 1149.1a-1993 Compliant Boundary-Scan Interface TDI (Test Data Input) TMS (Test Mode Select) TCK (Test Clock Input) TDO (Test Data Output) TRST (Test Reset) 8.9 Using Data-Bus Write-Only The 750GX supports split-transaction pipelined transactions. It supports a limited out-of-order capability for its own pipelined transactions through the data-bus write-only (DBWO) signal.
  • Page 321 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Note that although the 750GX can pipeline any write transaction behind the read transaction, special care should be used when using the enveloped write feature. It is envisioned that most system implementations will not need this capability;...
  • Page 322 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Bus Interface Operation gx_08.fm.(1.2) Page 322 of 377 March 27, 2006...
  • Page 323: L2 Cache

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 9. L2 Cache This chapter describes the 750GX microprocessor‘s implementation of the 1-MB L2 cache. Note: The L2 cache is initially disabled following a power-on or hard reset. Before enabling the L2 cache, configuration parameters must be set in the L2 Cache Control Register (L2CR), and the L2 tags must be globally invalidated.
  • Page 324: Table 9-1. Interpretation Of Lru Bits

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor If multiple read requests from the L1 caches are pending, the L2 cache can perform hit-under-miss opera- tions, supplying the available instruction or data while a bus transaction for previous L2 cache misses is being performed.
  • Page 325: Table 9-2. Modification Of Lru Bits

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Whenever a way in the set is referenced, the LRU bits are updated. The new value of the LRU bits depends on the old value, which way is currently being accessed, and whether the operation is an invalidation or a load/store.
  • Page 326 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 9-3. Effect of Locked Ways on LRU Interpretation (Page 2 of 2) LRU Bits Lock Bits LRU Way x011 xxx0 xx01 0x11 x011 L2 Cache gx_09.fm.(1.2) Page 326 of 377...
  • Page 327: Figure 9-1. L2 Cache

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 9-1. L2 Cache Load Store L1 Data Cache L1 Data Instruction Cache Castout, Reload Critical Cache Single Beat Stores Word Reload 64-bit 256-bit 256-bit Store Castout Reload Queue Queue Snoop...
  • Page 328 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The execution of the Store Word Conditional Indexed (stwcx.) instruction results in single-beat writes from the L1 data cache. These single-beat writes are processed by the L2 cache according to hit/miss status, L1 and L2 write-through configuration, and reservation-active status.
  • Page 329: L2 Cache Control Register (L2Cr)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 9.3 L2 Cache Control Register (L2CR) The L2 Cache Control Register is used to configure and enable the L2 cache. The L2CR is a supervisor-level read/write, implementation-specific register that is accessed as Special Purpose Register (SPR) 1017. The contents of the L2CR are cleared during power-on reset.
  • Page 330: L2 Cache Used As On-Chip Memory

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 9.6 L2 Cache Used as On-Chip Memory The L2 cache can be configured to be unlocked, partially locked, or completely locked. When configured to be unlocked, the L2 cache is 4-way set-associative, with 32 bytes per sector, two sectors per block. When configured to be completely locked, the L2 cache is a 1-MB on-chip memory (OCM) that is explicitly managed by software.
  • Page 331: Loading The Locked L2 Cache

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 9.6.1.1 Loading the Locked L2 Cache Contents are loaded into the L2 cache simply by executing load instructions to cacheable addresses that miss in the L1. Note that instructions to be locked in the L2 cache are loaded as data. Only one access to each 32-byte cache block is needed to allocate the entire block in the cache.
  • Page 332: Data-Only And Instruction-Only Modes

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The dcbz instruction has no effect on the L2-cache state, whether the state is locked or not. The dcbi instruc- tion causes invalidation of the block in the case of an L2 hit, for both normal and locked caches.
  • Page 333: L2 Cache Testing

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 9.8.2 L2 Cache Testing A typical test for verifying the proper operation of the 750GX microprocessor’s L2-cache memory follows this sequence: 1. Initialize the L2 test sequence by disabling address translation to invoke the default WIMG setting (0011).
  • Page 334 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor L2 Cache gx_09.fm.(1.2) Page 334 of 377 March 27, 2006...
  • Page 335: Power And Thermal Management

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 10. Power and Thermal Management The 750GX microprocessor is specifically designed for low-power operation. It provides both automatic and program-controlled power reduction modes for progressive reduction of power consumption. It also provides a thermal assist unit (TAU) to allow on-chip thermal measurement, allowing sophisticated thermal manage- ment for high-performance portable systems.
  • Page 336: Figure 10-1. 750Gx Power States

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 10-1. 750GX Power States Full Doze Sleep allow snoop T1: HID0(Doze) = 1 and MSR(POW) 0 → 1 T2: HRESET, SRESET, INT, SMI, MCP, DEC, PFM, machine-check interrupts, thermal-management interrupt T3: HID0(Nap) = 1 and MSR(POW) 0 →...
  • Page 337: Power Management Modes

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 10.2.1 Power Management Modes The following sections describe the characteristics of the 750GX’s power management modes, the require- ments for entering and exiting the various modes, and the system capabilities provided by the 750GX while the power management modes are active.
  • Page 338 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 750GX will then be able respond to a snoop cycle. Assertion of QACK following the snoop cycle will again disable the 750GX’s snoop capability. The 750GX’s power dissipation while in nap mode with QACK deas- serted is the same as the power dissipation while in doze mode.
  • Page 339: Sleep Mode

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 10.2.1.4 Sleep Mode Sleep mode consumes the least amount of power of the four modes since all functional units are disabled. To conserve the maximum amount of power, the PLL can be disabled by placing the PLL_CFG signals in the PLL bypass mode, and disabling SYSCLK.
  • Page 340: Power Management Software Considerations

    PLL1 configuration of clock off, and the selection of the medium frequency range. As stated in the PowerPC 750GX RISC Microprocessor Datasheet, HRESET must be asserted during power up long enough for the PLLs to lock and for the internal hardware to be reset. Once this timing is satisfied, HRESET can be negated.
  • Page 341: Configuration Restriction On Frequency Transitions

    HID1[PR1] and HID1[PC1] to the appropriate values. Next, wait for PLL1 to lock. The lock time is the same for both PLLs and is provided in the PowerPC 750GX RISC Microprocessor Datasheet. Finally, set HID1[PS] to a 1 to initiate the transition from PLL0 to PLL1 as the source of the processor clocks. From the time the HID1 Register is updated to select the new PLL, the transition to the new clock frequency will complete within three bus cycles.
  • Page 342: Dual Pll Implementation

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 10.3.3 Dual PLL Implementation Switching between the two PLLs on the 750GX is intended to be a seamless, 3-cycle operation. As shown in Figure 10-2, the two PLL outputs will feed a multiplexer (MUX), controlled by a signal from the PLL select logic.
  • Page 343: Thermal Assist Unit

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 10-3. Dual PLL Switching Example, 3X to 4X SYSCLK GCLK clk blocked 10.4 Thermal Assist Unit With the increasing power dissipation of high-performance processors and operating conditions that span a wider range of temperatures than desktop systems, thermal management becomes an essential part of system design to ensure reliable operation of portable systems.
  • Page 344: Thermal Assist Unit Operation

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Figure 10-4. Thermal Assist Unit Block Diagram Thermal Sensor Thermal Interrupt Interrupt Control Request (0x1700) Thermal Sensor Control Logic Decoder Latch THRM1 THRM2 The TAU provides thermal control by periodically comparing the 750GX’s junction temperature against user- programmed thresholds, and generating a thermal-management interrupt if the threshold values are crossed.
  • Page 345: Tau Single-Threshold Mode

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 10.4.2.1 TAU Single-Threshold Mode When the TAU is configured for single-threshold mode, either THRM1 or THRM2 can be used to contain the threshold value, and a thermal-management interrupt is generated when the threshold value is crossed. To...
  • Page 346: Tau Dual-Threshold Mode

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 10-3. Valid THRM1 and THRM2 Bit Settings (Page 2 of 2) Description The junction temperature is less than the threshold, and, as a result, the thermal- management interrupt is not generated for TIE = 1.
  • Page 347: Power Saving Modes And Tau Operation

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 10.4.2.4 Power Saving Modes and TAU Operation The static power saving modes provided by the 750GX (the nap, doze, and sleep modes) allow the tempera- ture of the processor to be lowered quickly, and can be invoked through the use of the TAU and associated thermal-management interrupt.
  • Page 348: Table 10-4. Ictc Bit Field Settings

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor The bit field settings of the ICTC SPR are shown in Table 10-4 on page 348. Table 10-4. ICTC Bit Field Settings Bits Name Description Bits reserved for future use. The system software should always write zeros to these bits when writing to...
  • Page 349: Performance Monitor And System Related Features

    (and perhaps partition them) and that structure and distribute data optimally. • To improve processor architecture, the detailed behavior of the PowerPC 750GX’s structure must be known and understood in many software environments. Some environments might not be easily charac- terized by a benchmark or trace.
  • Page 350: Special-Purpose Registers Used By Performance Monitor

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor As a result of a performance-monitor exception being taken, the action taken depends on the programmable events. To help track which part of the code was being executed when an exception was signaled, the address of the last completed instruction during that cycle is saved in the Sampled Instruction Address (SIA) register.
  • Page 351: Performance-Monitor Registers

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 11.2.1 Performance-Monitor Registers This section describes the registers used by the performance monitor. 11.2.1.1 Monitor Mode Control Register 0 (MMCR0) The Monitor Mode Control Register 0 (MMCR0) is a 32-bit SPR provided to specify events to be counted and recorded.
  • Page 352: Table 11-2. Pmc1 Events-Mmcr0[19:25] Select Encodings

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Software is expected to use the mtspr instruction to explicitly set PMC to nonoverflowed values. Setting an overflowed value might cause an erroneous exception. For example, if both MMCR0[ENINT] and either PMC1INTCONTROL or PMCINTCONTROL are set and the mtspr instruction loads an overflow value, an interrupt signal might be generated without event counting having taken place.
  • Page 353: Table 11-4. Pmc3 Events-Mmcr1[0:4] Select Encodings

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 11-3. PMC2 Events—MMCR0[26:31] Select Encodings (Page 2 of 2) Encoding Description 00 0101 Counts L1 instruction-cache misses. 00 0110 Counts ITLB misses. 00 0111 Counts L2 instruction misses. 00 1000 Counts branches predicted or resolved not taken.
  • Page 354: User Performance-Monitor Counter Registers (Upmc1-Upmc4)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 11-4. PMC3 Events—MMCR1[0:4] Select Encodings (Page 2 of 2) Encoding Description 1 0000 Number of branches in the second speculative stream that resolve correctly. 1 0001 Number of cycles the BPU stalls due to LR or CR unresolved dependencies.
  • Page 355: Sampled Instruction Address Register (Sia)

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 11.2.1.7 Sampled Instruction Address Register (SIA) The Sampled Instruction Address Register (SIA) is a supervisor-level register that contains the effective address of an instruction executing at or around the time that the processor signals the performance-monitor interrupt condition.
  • Page 356: Event Selection

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 11.4 Event Selection Event selection is handled through MMCR0 and MMCR1. • The four event-select fields in MMCR0 and MMCR1 are: – MMCR0[19:25] PMC1SELECT PMC1 input selector. 128 events selectable; 25 defined. See Table 11-2 on page 352.
  • Page 357: Debug Support

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 11.6 Debug Support 11.6.1 Overview The 750GX provides the following debug support features: • Branch trace • Single step instruction trace • Instruction-address breakpoint • Data-address breakpoint • Externally triggered soft stop The trace mode allows either a single step trace if MSR[SE] = 1 or a branch trace if MSR[BE] = 1.
  • Page 358: Figure 11-1. 750Gx Ieee 1149.1A-1993/Cop Organization

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor • Internal registers (such as the general-purpose, floating-point, and processor version registers) • Data cache • Instruction cache • L2 cache • L2 tag • Data tag • Instruction tag • Data translation lookaside buffer (TLB) •...
  • Page 359: Resets

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 11.8 Resets The 750GX supports two types of resets: a hard and a soft reset. 11.8.1 Hard Reset The hard reset is triggered by the assertion of the hard reset pin, HRESET. The HRESET pin is asserted by several sources: •...
  • Page 360: Reset Sequence

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 11.8.3 Reset Sequence Figure 11-2. Reset Sequence Hard Reset Soft Reset Scan in 0s > 255 clocks Hard Reset? JTAG_IR=FFRZ? Stop Chip Clks Perform RISCWatch Functions RISCWatch cmd = RESUME? Chip Clks Running...
  • Page 361: Checkstops

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 11.9 Checkstops A checkstop causes the processor to halt and assert the checkstop output pin, CKSTP_OUT. Once the 750GX enters a checkstop state, only a hard reset can clear the processor.
  • Page 362: Open-Collector-Driver States During Checkstop

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Table 11-7 shows the control bits for HID2. Table 11-7. HID2 Checkstop Control Bits Hard Bits Field Name Reset Description State ICPE Enable L1 instruction-cache or instruction-tag parity checking. DCPE Enable L1 data-cache or data-tag parity checking.
  • Page 363: 750Gx Parity

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 11.10 750GX Parity Parity is implemented for the following arrays: instruction cache, instruction tag, data cache, data tag, and L2 tag. All parity errors, when parity is enabled, result in either a machine-check or checkstop interrupt that is not recoverable.
  • Page 364: Parity Control And Status

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor 11.10.1 Parity Control and Status Parity is enabled with the Hardware-Implementation-Dependent Register 2 (HID2). For a diagram of this register and a description of its fields, see Hardware-Implementation-Dependent Register 2 (HID2) on page 71.
  • Page 365: Acronyms And Abbreviations

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Acronyms and Abbreviations block-address translation branch history table BIST built-in self test bus interface unit branch processing unit BSDL Boundary-Scan Description Language BTIC branch target instruction cache BUID bus unit ID...
  • Page 366 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Floating Point Register FPSCR Floating-Point Status and Control Register floating-point unit General Purpose Register HIDn Hardware-Implementation-Dependent Register IABR Instruction Address Breakpoint Register IBAT instruction BAT ICTC Instruction Cache Throttling Control Register...
  • Page 367 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor not a number no-op no operation operating environment architecture processor identification tag phase-locked loop PLRU pseudo least recently used PMCn Performance-Monitor Counter Registers power-on reset POWER Performance Optimized with Enhanced RISC architecture...
  • Page 368 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor THRM n Thermal-Management Registers translation lookaside buffer transistor-to-transistor logic UIMM unsigned immediate value UISA user instruction set architecture UMMCRn User Monitor Mode Control Registers UPMCn User Performance-Monitor Counter Registers USIA User Sampled Instruction Address Register...
  • Page 369: Index

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Index address calculation condition register logical list of instructions system linkage trap Branch prediction AACK (address acknowledge) signal Branch processing unit ABB (address bus busy) signal branch instruction timing Address bus...
  • Page 370 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor L2 interface DCFI, DCE, DLOCK bits cache global invalidation organization cache initialization Data organization in memory cache testing Data transfers dcbi alignment eieio burst ordering operation eciwx and ecowx instructions, alignment stwcx.
  • Page 371 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor register settings doze bit DPM enable bit SRR0/SRR1 nap bit reset exception HID1 returning from an exception handler description summary table PLL configuration system call exception HRESET (hard reset) signal terminology...
  • Page 372 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor integer lwarx/stwcx. support byte reverse instructions floating-point move floating-point store integer load integer multiple Machine check exception integer store MCP (machine check interrupt) signal memory synchronization MEI protocol string instructions hardware considerations...
  • Page 373 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor PowerPC architecture operating environment architecture (OEA) user instruction set architecture (UISA) exception mechanism virtual environment architecture (VEA) memory management specifications Priorities, exception registers Process switching Operand conventions Processor control instructions Operand placement and performance...
  • Page 374 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor DABR SR manipulation instructions Segmented memory model, see Memory management unit DSISR Serializing instructions Shift/rotate instructions HID0 SIA (sampled instruction address) register HID1 Signals IABR AACK ICTC L2CR address arbitration MMCR0...
  • Page 375 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Stall, definition description Static branch prediction invalidate (tlbie instruction) stwcx. LRU replacement Superscalar, definition organization for ITLB and DTLB sync TLB miss and table search operation SYNC operation TLB invalidate Synchronization...
  • Page 376 User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Index 750gx_umIX.fm.(1.2) Page 376 of 377 March 27, 2006...
  • Page 377: Revision Log

    User’s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Revision Log Revision Date Contents of Modification February 27, 2004 Initial release (version 1.0) (version 1.1) on page 26, added the following to the list under "2-stage load/store unit (LSU)." "4-entry load queue."...

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