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PowerPC 750GX
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IBM PowerPC 750GX User Manual
Risc microprocessor
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
List of Figures
List of Tables
About this Manual
Who Should Read this Manual
Related Publications
Conventions Used in this Manual
Using this Manual with the Programming Environments Manual
1 Powerpc 750GX Overview
750GX Microprocessor Overview
Figure 1-1. 750GX Microprocessor Block Diagram
750GX Microprocessor Features
Instruction Flow
Branch Processing Unit (BPU)
Instruction Queue and Dispatch Unit
Completion Unit
Floating-Point Unit (FPU)
Independent Execution Units
Integer Units (Ius)
Load/Store Unit (LSU)
Memory Management Units (Mmus)
System Register Unit (SRU)
On-Chip Level 1 Instruction and Data Caches
Figure 1-2. L1 Cache Organization
On-Chip Level 2 Cache Implementation
System Interface/Bus Interface Unit (BIU)
Figure 1-3. System Interface
Signals
Signal Configuration
Figure 1-4. 750GX Microprocessor Signal Groups
Clocking
750GX Microprocessor Implementation
Powerpc Registers and Programming Model
Table 1-1. Architecture-Defined Registers (Excluding Sprs)
Table 1-2. Architecture-Defined Sprs Implemented
Table 1-3. Implementation-Specific Registers
Instruction Set
Powerpc Instruction Set
750GX Microprocessor Instruction Set
On-Chip Cache Implementation
750GX Microprocessor Cache Implementation
Powerpc Cache Model
Exception Model
Powerpc Exception Model
750GX Microprocessor Exception Implementation
Table 1-4. 750GX Microprocessor Exception Classifications
Table 1-5. Exceptions and Conditions
Memory Management
Powerpc Memory-Management Model
750GX Microprocessor Memory-Management Implementation
Instruction Timing
Figure 1-5. Pipeline Diagram
Power Management
Thermal Management
Performance Monitor
2 Programming Model
Powerpc 750GX Processor Register Set
Register Set
Figure 2-1. Powerpc 750GX Microprocessor Programming Model-Registers
Table 2-1. Additional MSR Bits
Table 2-2. Additional SRR1 Bits
Powerpc 750GX-Specific Registers
Instruction Address Breakpoint Register (IABR)
Hardware-Implementation-Dependent Register 0 (HID0)
Hardware-Implementation-Dependent Register 1 (HID1)
Hardware-Implementation-Dependent Register 2 (HID2)
Performance-Monitor Registers
Instruction Cache Throttling Control Register (ICTC)
Thermal-Management Registers (Thrmn)
Thermal-Management Registers 1-2 (THRM1-THRM2)
Table 2-3. Valid THRM1/THRM2 Bit Settings
Thermal-Management Register 3 (THRM3)
Thermal-Management Register 4 (THRM4)
L2 Cache Control Register (L2CR)
Operand Conventions
Data Organization in Memory and Data Transfers
Alignment and Misaligned Accesses
Table 2-4. Memory Operands
Floating-Point Operand and Execution Models-UISA
Denormalized Number Support
Non-IEEE Mode (Nondenormalized Mode)
Floating-Point Storage Access Alignment
Optional Floating-Point Graphics Instructions
Table 2-5. Floating-Point Operand Data-Type Behavior
Time-Critical Floating-Point Operation
Table 2-6. Floating-Point Result Data-Type Behavior
Instruction Set Summary
Classes of Instructions
Defined Instruction Class
Definition of Boundedly Undefined
Illegal Instruction Class
Reserved Instruction Class
Addressing Modes
Memory Addressing
Memory Operands
Effective Address Calculation
Synchronization
Instruction Set Overview
Powerpc UISA Instructions
Integer Instructions
Table 2-7. Integer Arithmetic Instructions
Table 2-8. Integer Compare Instructions
Table 2-9. Integer Logical Instructions
Floating-Point Instructions
Table 2-10. Integer Rotate Instructions
Table 2-11. Integer Shift Instructions
Table 2-12. Floating-Point Arithmetic Instructions
Table 2-13. Floating-Point Multiply/Add Instructions
Table 2-14. Floating-Point Rounding and Conversion Instructions
Table 2-15. Floating-Point Compare Instructions
Table 2-16. Floating-Point Status and Control Register Instructions
Load-And-Store Instructions
Table 2-17. Floating-Point Move Instructions
Table 2-18. Integer Load Instructions
Table 2-19. Integer Store Instructions
Table 2-20. Integer Load-And-Store with Byte-Reverse Instructions
Table 2-21. Integer Load-And-Store Multiple Instructions
Table 2-22. Integer Load-And-Store String Instructions
Table 2-23. Floating-Point Load Instructions
Table 2-24. Floating-Point Store Instructions
Table 2-25. Store Floating-Point Single Behavior
Table 2-26. Store Floating-Point Double Behavior
Branch and Flow-Control Instructions
Table 2-27. Branch Instructions
Table 2-28. Condition Register Logical Instructions
Processor Control Instructions-UISA
System Linkage Instruction-UISA
Table 2-29. Trap Instructions
Table 2-30. System Linkage Instruction-UISA
Table 2-31. Move-To/Move-From Condition Register Instructions
Table 2-32. Move-To/Move-From Special-Purpose Register Instructions (UISA)
Table 2-33. Powerpc Encodings
Table 2-34. SPR Encodings for 750GX-Defined Registers (Mfspr)
Memory Synchronization Instructions-UISA
Powerpc VEA Instructions
Processor Control Instructions-VEA
Table 2-35. Memory Synchronization Instructions-UISA
Memory Synchronization Instructions-VEA
Table 2-36. Move-From Time Base Instruction
Memory Control Instructions-VEA
Table 2-37. Memory Synchronization Instructions-VEA
Table 2-38. User-Level Cache Instructions
Optional External Control Instructions
Table 2-39. External Control Instructions
Powerpc OEA Instructions
Processor Control Instructions-OEA
System Linkage Instructions-OEA
Table 2-40. System Linkage Instructions-OEA
Table 2-41. Move-To/Move-From Machine State Register Instructions
Table 2-42. Move-To/Move-From Special-Purpose Register Instructions (OEA)
Memory Control Instructions-OEA
Table 2-43. Supervisor-Level Cache-Management Instruction
Table 2-44. Segment Register Manipulation Instructions
Recommended Simplified Mnemonics
Table 2-45. Translation Lookaside Buffer Management Instruction
3 Instruction-Cache and Data-Cache Operation
Figure 3-1. Cache Integration
Data-Cache Organization
Figure 3-2. Data-Cache Organization
Instruction-Cache Organization
Memory and Cache Coherency
Memory/Cache Access Attributes (WIMG Bits)
Figure 3-3. Instruction-Cache Organization
MEI Protocol
Table 3-1. MEI State Definitions
Figure 3-4. MEI Cache-Coherency Protocol-State Diagram (WIM = 001)
MEI Hardware Considerations
Coherency Precautions in Multiprocessor Systems
Coherency Precautions in Single-Processor Systems
Atomic Memory References
Performed Loads and Stores
Powerpc 750GX-Initiated Load/Store Operations
Sequential Consistency of Memory Accesses
Cache Control
Cache-Control Parameters in HID0
Data-Cache Flash Invalidation
Enabling and Disabling the Data Cache
Locking the Data Cache
Cache-Control Instructions
Enabling and Disabling the Instruction Cache
Instruction-Cache Flash Invalidation
Locking the Instruction Cache
Data Cache Block Touch (Dcbt) and Data Cache Block Touch for Store (Dcbtst)
Data Cache Block Zero (Dcbz)
Data Cache Block Flush (Dcbf)
Data Cache Block Invalidate (Dcbi)
Data Cache Block Store (Dcbst)
Instruction Cache Block Invalidate (Icbi)
Cache Operations
Cache-Block-Replacement/Castout Operations
Figure 3-5. PLRU Replacement Algorithm
Cache Flush Operations
Table 3-2. PLRU Bit Update Rules
Table 3-3. PLRU Replacement Block Selection
Data-Cache Block-Fill Operations
Data-Cache Block-Push Operations
Instruction-Cache Block-Fill Operations
L1 Caches and 60X Bus Transactions
Figure 3-6. 750GX Cache Addresses
Read Operations and the MEI Protocol
Bus Operations Caused by Cache-Control Instructions
Table 3-4. Bus Operations Caused by Cache-Control Instructions (WIM = 001)
Snooping
Snoop Response to 60X Bus Transactions
Table 3-5. Response to Snooped Bus Transactions
Transfer Attributes
Table 3-6. Address/Transfer Attribute Summary
MEI State Transactions
Table 3-7. MEI State Transitions
4 Exceptions
Powerpc 750GX Microprocessor Exceptions
Table 4-1. Powerpc 750GX Microprocessor Exception Classifications
Table 4-2. Exceptions and Conditions
Exception Recognition and Priorities
Table 4-3. Exception Priorities
Exception Processing
Machine Status Save/Restore Register 0 (SRR0)
Machine Status Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
Enabling and Disabling Exceptions
Steps for Exception Processing
Table 4-4. IEEE Floating-Point Exception Mode Bits
Setting MSR[RI]
Returning from an Exception Handler
Process Switching
Exception Definitions
Table 4-5. MSR Setting Due to Exception
System Reset Exception (0X00100)
Table 4-6. System Reset Exception-Register Settings
Figure 4-1. SRESET Asserted During HRESET
Hard Reset
Soft Reset
Table 4-7. Settings Caused by Hard Reset
Machine-Check Exception (0X00200)
Table 4-8. HID0 Machine-Check Enable Bits
Machine-Check Exception Enabled (MSR[ME] = 1)
Table 4-9. Machine-Check Exception-Register Settings
Checkstop State (MSR[ME] = 0)
DSI Exception (0X00300)
External Interrupt Exception (0X00500)
ISI Exception (0X00400)
Alignment Exception (0X00600)
Program Exception (0X00700)
Decrementer Exception (0X00900)
Floating-Point Assist Exception (0X00E00)
Floating-Point Unavailable Exception (0X00800)
System Call Exception (0X00C00)
Trace Exception (0X00D00)
Performance-Monitor Interrupt (0X00F00)
Table 4-10. Performance-Monitor Interrupt Exception-Register Settings
Instruction Address Breakpoint Exception (0X01300)
System Management Interrupt (0X01400)
Table 4-11. Instruction Address Breakpoint Exception-Register Settings
Table 4-12. System Management Interrupt Exception-Register Settings
Table 4-13. Thermal-Management Interrupt Exception-Register Settings
Thermal-Management Interrupt Exception (0X01700)
Data Address Breakpoint Exception
Data Address Breakpoint Register (DABR)
Soft Stops
Exception Latencies
Summary of Front-End Exception Handling
Table 4-14. Front-End Exception Handling Summary
External Access Instructions
Timer Facilities
5 Memory Management
MMU Overview
Table 5-1. MMU Feature Summary
Figure 5-1. MMU Conceptual Block Diagram
Figure 5-2. Powerpc 750GX Microprocessor IMMU Block Diagram
Memory Addressing
MMU Organization
Figure 5-3. 750GX Microprocessor DMMU Block Diagram
Address-Translation Mechanisms
Figure 5-4. Address-Translation Types
Memory-Protection Facilities
Page History Information
Table 5-2. Access Protection Options for Pages
General Flow of MMU Address Translation
Figure 5-5. General Flow of Address Translation (Real-Addressing Mode and Block)
Real-Addressing Mode and Block-Address-Translation Selection
Figure 5-6. General Flow of Page and Direct-Store Interface Address Translation
Page-Address-Translation Selection
MMU Exceptions Summary
Table 5-3. Translation Exception Conditions
Table 5-4. Other MMU Exception Conditions for the 750GX Processor
MMU Instructions and Register Summary
Table 5-5. 750GX Microprocessor Instruction Summary-Control Mmus
Real-Addressing Mode
Table 5-6. 750GX Microprocessor MMU Registers
Block-Address Translation
Memory Segment Model
Page History Recording
Referenced Bit
Table 5-7. Table-Search Operations to Update History Bits-TLB Hit Case
Changed Bit
Scenarios for Referenced and Changed Bit Recording
Table 5-8. Model for Guaranteed R and C Bit Settings
Page Memory Protection
TLB Description
TLB Organization
Figure 5-7. Segment Register and DTLB Organization
TLB Invalidation
Page-Address-Translation Summary
Figure 5-8. Page-Address-Translation Flow-TLB Hit
Page Table-Search Operation
Figure 5-9. Primary Page Table Search
Figure 5-10. Secondary Page-Table-Search Flow
Page Table Updates
Segment Register Updates
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Title Page
IBM PowerPC 750GX and 750GL RISC Micro-
processor
User's Manual
Version 1.2
March 27, 2006
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