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Table 2·3. Hardware Implementation-Dependent Register
o
Bit Settings (Continued)
Bit
Description
18
Instruction cache lock
0
Nonnal operation
1
All misses are treated as cache-inhibited. Hits occur as nonnal. Snoop and
cache
operations continue to
work as nonnal. This is the only method for "deallocating" an entry.
19
Data cache lock
0
Nonnal operation
1
All misses are treated as cache-inhibited. Hits occur as nonnal. Snoop and cache operations continue to
work as nonnal. This
is
the only method for "deallocating" an entry. The dcbz instruction takes an
alignment exception if the data cache
is
locked when it
is
executed, provided the target address had
been translated correctly.
20
Instruction cache invalidate all
0
The instrudion cache is not invafidated.
1
When set, an invafidate operation Is Issued that marks the state of each dock in the instrudion cache as
invafid without writing back any modified lines to memory. Access to the cache is blocked during this
time. Accesses to the cache from the bus are signaled as a miss while the invafidate-all aperation is in
progress.
The bit is deared when the invalidation operation begins (usually the cyde Immediately following the
write
operation to the register). Note that the lnstrudion ca.Che must be enabled for the invalidation to occur.
21
Data cache invalidate aU
0
The
data cache Is not invalidated.
1
When set, an invalidate operation is issued that marks the state
of
each dock in the data cache as
invalid without writing back any modified fines
to memory. Access to the cache Is blocked during this
time. Accesses to the cache from the bus are signaled as a miss while the invafidate-all operation
is
in
progress.
The bit is deared when the invalidation operation begins (usually the cyde immediately following the write
operation to the register). Note that the data cache.must be enabled for the Invalidation to occur.
24
Serial
instrudion execution disable
0
The 604 executes one instruction at a time. The 604 does not post a trace exception after each
Instruction completes, as it would if MSR(SE] or MSR(BE] were set.
1
lnstrudion execution is
not
serialized.
29
Branch history table enable
0
The 604 uses static branch prediction as defined by the PowerPC architedure (UISA) for those branch
instructions that the BHT would have otherwise been used to predict (that is, those that use the CR as
the
only mechanism to detennine direction. For more information on static branch prediction, see
sedion "Conditional Branch Control," in Chapter 4 of
1118 Programming Environments Manual.
1
Allows the use of the 512-entry branch history table (BHT).
The BHT is initialized and disabled at power-on reset. The BHT is updated while
it
is
disabled, so it can be
initiaUzed before
It
is enabled.
2.1.2.4 Performance Monitor Registers
The remaining five registers defined for use with the 604 are used by the perfonnance
monitor. For more information about the performance monitor, see Chapter 9,
"Performance Monitor."
2.1.2.4.1 Monitor Mode Control Register 0 (MMCRO)
The monitor mode control register 0 (MMCRO) is a 32-bit SPR (SPR 952) whose bits are
partitioned into bit fields that determine the events to be counted and recorded. The
selection of allowable combinations of events causes the counters to operate concurrently.
Chapter 2. PowerPC 604 Pl'OC8880I' Programming Model
2-11
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